K20P48M50SF0 Datasheet, PDF (35/60 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

Num
EP1
EP1a
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Peripheral operating requirements and behaviors
Table 22. EzPort switching specifications (continued)
Description
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Min.
—
—
2 x t_{EZP_CK}
5
5
2
5
—
0
—
Max.
f_SYS/2
f_SYS/8
—
—
—
—
—
17
—
12
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP3
EP4
EP2
EP9
EP8
EP7
EP5
EP6
Figure 9. EzPort Timing Diagram
6.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.6 Analog
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
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