K20P48M50SF0 Datasheet, PDF (23/60 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

6.1.1
Peripheral operating requirements and behaviors
JTAG electricals
Table 12. JTAG voltage range electricals
Symbol
J1
J2
J3
Description
Operating voltage
TCLK frequency of operation
• JTAG
• CJTAG
TCLK cycle period
TCLK clock pulse width
• JTAG
• CJTAG
J4
TCLK rise and fall times
J5
TMS input data setup time to TCLK rise
• JTAG
• CJTAG
J6
TDI input data setup time to TCLK rise
J7
TMS input data hold time after TCLK rise
• JTAG
• CJTAG
J8
TDI input data hold time after TCLK rise
J9
TCLK low to TMS data valid
• JTAG
• CJTAG
J10
TCLK low to TDO data valid
J11
Output data hold/invalid time after clock edge¹
Min.
2.7
—
—
1/J1
100
200
—
53
112
8
3.4
3.4
3.4
—
—
—
—
Max.
5.5
10
5
—
—
—
1
—
—
—
—
—
—
48
85
48
3
Unit
V
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1. They are common for JTAG and CJTAG. Input transition = 1 ns and Output load = 50pf
TCLK (input)
J2
J3
J3
J4
J4
Figure 4. Test clock input timing
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
Freescale Semiconductor, Inc.
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