K20P48M50SF0 Datasheet, PDF (20/60 Pages) Freescale Semiconductor, Inc – K20 Sub-Family

General
Table 9. Device clock specifications (continued)
Symbol
f_FLASH
f_ERCLK
f_{LPTMR_pin}
f_{LPTMR_ERCLK}
f_{I2S_MCLK}
f_{I2S_BCLK}
Description
Flash clock
External reference clock
LPTMR clock
LPTMR external reference clock
I2S master clock
I2S bit clock
Min.
—
—
—
—
—
—
Max.
1
16
25
16
12.5
4
Unit
MHz
MHz
MHz
MHz
MHz
MHz
Notes
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any
other module.
5.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, and I²C signals.
Table 10. General switching specifications
Symbol
Description
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter enabled) — Asynchronous path
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External reset pulse width (digital glitch filter disabled)
Mode select (EZP_CS) hold time after reset
deassertion
Port rise and fall time (high drive strength)
• Slew disabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
• Slew enabled
• 1.71 ≤ V_DD ≤ 2.7V
• 2.7 ≤ V_DD ≤ 3.6V
Min.
1.5
100
50
100
2
—
—
—
—
Max.
—
—
—
—
—
Unit
Bus clock
cycles
ns
ns
ns
Bus clock
cycles
Notes
1, 2
3
3
3
4
13
ns
ns
7
ns
36
ns
24
Table continues on the next page...
K20 Sub-Family Data Sheet, Rev. 4 5/2012.
20
Freescale Semiconductor, Inc.