S9S08SL8F1CTJ Datasheet, PDF (345/356 Pages) Freescale Semiconductor, Inc – provides the functional version of the on-chip modules

Appendix A Electrical Characteristics
Table A-12. ADC Characteristics (continued)
Characteristic
Conditions
C Symb
Min
Typ¹
Max
Unit
Comment
Temp sensor
slope
-40°C to 25°C
25°C to 125°C
D
m
—
3.266
— mV/°C
—
3.638
—
Temp sensor
voltage
25°C
D V_TEMP25
—
1.396
—
V
1 _{Typical values assume VDD = 5.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference only}
and are not tested in production.
2 _{1 LSB = (VREFH - VREFL)/2}N
3 _{Based on input pad leakage current. Refer to pad electricals.}
A.12 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
A.12.1 Control Timing
Table A-13. Control Timing
Num C
Rating
Symbol
Min
Typ¹
Max Unit
1
D Bus frequency (t_cyc = 1/f_Bus)
f_Bus
dc
—
20
MHz
2 D Internal low power oscillator period
t_LPO
800
1500 μs
3 D _{External reset pulse width}²
t_extrst
100
—
ns
4 D _{Reset low drive}³
t_rstdrv
66 x t_cyc
—
ns
Pin interrupt pulse width
5 D Asynchronous path²
Synchronous path⁴
Port rise and fall time —
Low output drive (PTxDS = 0) (load = 50 pF)⁵
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
6
C
Port rise and fall time —
High output drive (PTxDS = 1) (load = 50 pF)⁵
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
t_ILIH, t_IHIL
100
—
1.5 x t_cyc
t_Rise, t_Fall
—
40
—
75
t_Rise, t_Fall
—
11
—
35
—
ns
—
ns
—
—
ns
—
1 _{Typical values are based on characterization data at VDD = 5.0V, 25°C unless otherwise stated.}
2 _{This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to}
override reset requests from internal sources.
3 _{When any reset is initiated, internal circuitry drives the reset pin low for about 66 cycles of tcyc. After POR reset, the bus clock}
frequency changes to the untrimmed DCO frequency (f_reset = (f_{dco_ut})/4) because TRIM is reset to 0x80 and FTRIM is reset
to 0, and there is an extra divide-by-two because BDIV is reset to 0:1. After other resets trim stays at the pre-reset value.
4 _{This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or}
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
5 _{Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40°C to 125°C.}
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
347