S9S08SL8F1CTJ Datasheet, PDF (179/356 Pages) Freescale Semiconductor, Inc – provides the functional version of the on-chip modules

Inter-Integrated Circuit (S08IICV2)
After a repeated start condition (Sr), all other slave devices also compare the first seven bits of the first
byte of the slave address with their own addresses and test the eighth (R/W) bit. However, none of them
are addressed because R/W = 1 (for 10-bit devices) or the 11110XX slave address (for 7-bit devices) does
not match.
S
Slave Address
1st 7 bits
R/W
Slave Address
A1
2nd byte
A2
Sr
Slave Address
1st 7 bits
R/W
A3 Data A ... Data A P
11110 + AD10 + AD9 0
AD[8:1]
11110 + AD10 + AD9 1
Table 11-11. Master-Receiver Addresses a Slave-Transmitter with a 10-bit Address
After the master-receiver has sent the first byte of the 10-bit address, the slave-transmitter sees an IIC
interrupt. Software must ensure the contents of IICD are ignored and not treated as valid data for this
interrupt.
11.4.3 General Call Address
General calls can be requested in 7-bit address or 10-bit address. If the GCAEN bit is set, the IIC matches
the general call address as well as its own slave address. When the IIC responds to a general call, it acts as
a slave-receiver and the IAAS bit is set after the address cycle. Software must read the IICD register after
the first byte transfer to determine whether the address matches is its own slave address or a general call.
If the value is 00, the match is a general call. If the GCAEN bit is clear, the IIC ignores any data supplied
from a general call address by not issuing an acknowledgement.
11.5 Resets
The IIC is disabled after reset. The IIC cannot cause an MCU reset.
11.6 Interrupts
The IIC generates a single interrupt.
An interrupt from the IIC is generated when any of the events in Table 11-12 occur, provided the IICIE bit
is set. The interrupt is driven by bit IICIF (of the IIC status register) and masked with bit IICIE (of the IIC
control register). The IICIF bit must be cleared by software by writing a 1 to it in the interrupt routine. You
can determine the interrupt type by reading the status register.
Table 11-12. Interrupt Summary
Interrupt Source
Complete 1-byte transfer
Match of received calling address
Arbitration Lost
Status
TCF
IAAS
ARBL
Flag
IICIF
IICIF
IICIF
Local Enable
IICIE
IICIE
IICIE
11.6.1 Byte Transfer Interrupt
The TCF (transfer complete flag) bit is set at the falling edge of the ninth clock to indicate the completion
of byte transfer.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
179