S9S08SL8F1CTJ Datasheet, PDF (115/356 Pages) Freescale Semiconductor, Inc – provides the functional version of the on-chip modules

Chapter 8
Internal Clock Source (S08ICSV2)
8.1 Introduction
The internal clock source (ICS) module provides clock source choices for the MCU. The module contains
a frequency-locked loop (FLL) as a clock source that is controllable by either an internal or an external
reference clock. The module can provide this FLL clock or either of the internal or external reference
clocks as a source for the MCU system clock. There are also signals provided to control a low power
oscillator (XOSC) module to allow the use of an external crystal/resonator as the external reference clock.
Whichever clock source is chosen, it is passed through a reduced bus divider (BDIV) which allows a lower
final output clock frequency to be derived.
The bus frequency is half of the ICSOUT frequency. After reset, the ICS is configured for FEI mode and
BDIV resets to 01 to introduce an extra divide-by-two before ICSOUT. Therefore, the bus frequency is
f_dco/4. At POR, the TRIM and FTRIM are reset to 0x80 and 0, respectively. Therefore, the dco frequency
is f_{dco_ut}. For other resets, the trim settings keep the value that was present before the reset.
NOTE
Refer to Section 1.3, “System Clock Distribution”, for a detailed view of the
distribution of clock sources throughout the MCU.
8.1.1 Module Configuration
When the internal reference is enabled in stop mode (IREFSTEN = 1), the voltage regulator must also be
enabled in stop mode by setting the LVDE and LVDSE bits in the SPMSC1 register.
Figure 8-1 shows the MC9S08EL32 block diagram with the ICS highlighted.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
115