S9S08SL8F1CTJ Datasheet, PDF (226/356 Pages) Freescale Semiconductor, Inc – provides the functional version of the on-chip modules

Because perfect conditions are almost impossible to attain, more robust values must be chosen for bit rates.
For reliable communication, it is best to ensure that a bit time is no smaller 2x–3x longer than the filter
delay on the digital receive filter. This is true in LIN or BTM mode and ensures that valid data bits which
have been shortened due to ground shift, asymmetrical rise and fall times, etc., are accepted by the filter
without exception. This would translate to 2x to 3x reduction in the maximum speeds shown in
Table 12-14. Recommended maximum bit rates are shown in Table 12-15, and ensure that a single bit time
is at least twice the length of one filter delay value. If system noise is not adequately filtered out it might
be necessary to change the prescaler of the filter and lower the bit rate of the communication. If valid
communications are being absorbed by the filter, corrective action must be taken to ensure that either the
bit rate is reduced or whatever physical fault is causing bit times to shorten is corrected (ground offset,
asymmetrical rise/fall times, insufficient physical layer supply voltage, etc.).
Table 12-15. Recommended Maximum Bit Rates for BTM Operation Due to Digital Filter
SLIC
Clock
(MHz)
20
18
16
14
12
10
8
6
4
2
Maximum BTM Bit Rate (kbps)
RXFP = ÷8 RXFP = ÷7 RXFP = ÷6 RXFP = ÷5 RXFP = ÷4 RXFP = ÷3 RXFP = ÷2 RXFP = ÷1
78.125
70.313
62.500
54.688
46.875
39.063
31.250
23.438
15.625
7.813
89.286
80.357
71.429
62.500
53.571
44.643
35.714
26.786
17.857
8.929
104.167
93.750
83.333
72.917
62.500
52.083
41.667
31.250
20.833
10.417
120.000
112.500
100.000
87.500
75.000
62.500
50.000
37.500
25.000
12.500
120.000
120.000
120.000
109.375
93.750
78.125
62.500
46.875
31.250
15.625
120.000
120.000
120.000
120.000
120.000
104.167
83.333
62.500
41.667
20.833
120.000
120.000
120.000
120.000
120.000
120.000
120.000
93.750
62.500
31.250
120.000
120.000
120.000
120.000
120.000
120.000
120.000
120.000
120.000
62.500
12.6.17 Oscillator Trimming with SLIC
SLCACT can be used as an indicator of LIN bus activity. SLCACT tells the user that the SLIC is currently
processing a message header (therefore synchronizing to the bus) or processing a message frame
(including checksum). Therefore, at idle times between message frames or during a message frame which
has been marked as a “don’t care” by writing IMSG, it is possible to trim the oscillator circuit of the MCU
with no impact to the LIN communications.
It is important to note the exact mechanisms with which the SLIC sets and clears SLCACT. Any falling
edge which successfully passes through the digital receive filter will cause SLCACT to become set. This
might even include noise pulses, if they are of sufficient length to pass through the digital RX filter.
Although in these cases SLCACT is becoming set on a noise spike, it is very probable that noise of this
nature will cause other system issues as well such as corruption of the message frame. The software can
then further qualify if it is appropriate to trim the oscillator.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
228
Freescale Semiconductor