S9S08SL8F1CTJ Datasheet, PDF (218/356 Pages) Freescale Semiconductor, Inc – provides the functional version of the on-chip modules

The LIN 1.3 and earlier specifications transmit a checksum byte in the “CHECKSUM FIELD” of the LIN
message frame. This CHECKSUM FIELD contains the inverted modulo-256 sum over all data bytes. The
sum is calculated by an “ADD with Carry” where the carry bit of each addition is added to the least
significant bit (LSB) of its resulting sum. This guarantees security also for the MSBs of the data bytes. The
sum of modulo-256 sum over all data bytes and the checksum byte must be ‘0xFF’.
An optional checksum calculation can also be performed on a LIN data frame which is very similar to the
LIN 1.3 calculation, but with one important distinction. This enhanced calculation simply includes the
identifier field as the first value in the calculation, whereas the LIN 1.3 calculation begins with the least
significant byte of the data field (which is the first byte to be transmitted on the bus). This enhanced
calculation further ensures that the identifier field is correct and ties the identifier and data together under
a common calculation, ensuring greater reliability.
In the SLIC module, either checksum calculation can be performed on any given message frame by simply
writing or clearing CHKMOD in SLCDLC, as desired, when the identifier for the message frame is
decoded. The appropriate calculation for each message frame should be decided at system design time and
documented in the LIN description file, indicating to the user which calculation to use for a particular
identifier.
12.6.14 High-Speed LIN Operation
High-speed LIN operation does not necessarily require any reconfiguration of the SLIC module,
depending upon what maximum LIN bit rate is desired. Several factors affect the performance of the SLIC
module at LIN speeds higher than 20 kbps, all of which are functions of the speed of the SLIC clock and
the prescaler of the digital filter. The tightest constraint comes from the need to maintain ±1.5% accuracy
with the master node timing. This requires that the SLIC module be able to sample the incoming data
stream accurately enough to guarantee that accuracy. Table 12-12 shows the maximum LIN bit rates
allowable to maintain this accuracy.
Table 12-12. Maximum Theoretical LIN Bit Rates for High-Speed Operation¹
SLIC Clock
(MHz)
20
18
16
14
12
10
8
6
4
2
Max LIN Speed w/ 1%
Accuracy (bps)
200,000
180,000
160,000
140,000
120,000
100,000
80,000
60,000
40,000
20,000
Max LIN Speed w/ 1.5%
Accuracy (bps)
300,000
270,000
240,000
210,000
180,000
150,000
120,000
90,000
60,000
30,000
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
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Freescale Semiconductor