S9S08SL8F1CTJ Datasheet, PDF (228/356 Pages) Freescale Semiconductor, Inc – provides the functional version of the on-chip modules

12.6.18 Digital Receive Filter
The receiver section of the SLIC module includes a digital low-pass filter to remove narrow noise pulses
from the incoming message. A block diagram of the digital filter is shown in Figure 12-22.
RX DATA
FROM
SLCRX PIN
INPUT
SYNC
D
Q
4-BIT UP/DOWN COUNTER
DIGITAL RX FILTER
PRESCALER (RXFP)
UP/DOWN
HOLD
OUT ⁴
EDGE &
COUNT
D
Q
COMPARATOR
FILTERED
RX DATA OUT
Figure 12-22. SLIC Module Rx Digital Filter Block Diagram
SLIC CLOCK
12.6.18.1 Digital Filter Operation
The clock for the digital filter is provided by the SLIC Interface clock. At each positive edge of the clock
signal, the current state of the receiver input signal from the SLCRX pad is sampled. The SLCRX signal
state is used to determine whether the counter should increment or decrement at the next positive edge of
the clock signal.
The counter will increment if the input data sample is high but decrement if the input sample is low. The
counter will thus progress up towards the highest count value (determined by RXFP bit settings), on
average, the SLCRX signal remains high or progress down towards ‘0’ if, on average, the SLCRX signal
remains low. The final counter value which determines when the filter will change state is generated by
shifting the RXFP value right three positions and bitwise OR-ing the result with the value 0x0F. For
example, a prescale setting of divide by 3 would give a count value of 0x2F.
When the counter eventually reaches this value, the digital filter decides that the condition of the SLCRX
signal is at a stable logic level 1 and the data latch is set, causing the filtered Rx data signal to become a
logic level 1. Furthermore, the counter is prevented from overflowing and can only be decremented from
this state.
Alternatively, when the counter eventually reaches the value ‘0’, the digital filter decides that the condition
of the SLCRX signal is at a stable logic level 0 and the data latch is reset, causing the filtered Rx data signal
to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only be
incremented from this state.
The data latch will retain its value until the counter next reaches the opposite end point, signifying a
definite transition of the SLCRX signal.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
230
Freescale Semiconductor