S9S08SL8F1CTJ Datasheet, PDF (195/356 Pages) Freescale Semiconductor, Inc – provides the functional version of the on-chip modules

7
6
5
4
3
2
R SLCACT
0
INITACK
0
0
0
W
Reset
0
0
1
0
0
0
= Unimplemented or Reserved
Figure 12-8. SLIC Status Register (SLCS)
1
0
0
SLCF
0
0
Table 12-6. SLCS Field Descriptions
Field
Description
7
SLCACT¹
SLIC Active (Oscillator Trim Blocking Semaphore) — SLCACT is used to indicate if it is safe to trim the
oscillator based upon current SLIC activity in LIN mode. This bit indicates that the SLIC module might be currently
receiving a message header, synchronization byte, ID byte, or sending or receiving data bytes. This bit is
read-only. This bit has no meaning in BTM mode (BTM =1).
0 SLIC module not active (safe to trim oscillator) SLCACT is cleared by the SLIC module only upon assertion of
the RX Message Buffer Full Checksum OK (SLCSV = 0x10) or the TX Message Buffer Empty Checksum
Transmitted (SLCSV = 0x08) interrupt sources.
1 SLIC module activity (not safe to trim oscillator)
SLCACT is automatically set to 1 if a falling edge is seen on the SLCRX pin and has successfully been passed
through the digital RX filter. This edge is the potential beginning of a LIN message frame.
5
INITACK
Initialization Mode Acknowledge — INITACK indicates whether the SLIC module is in the reset mode as a
result of writing INITREQ in SLCC1. INITACK = 1 causes all SLIC register bits (except SLCWCM: write once) to
be held in their reset state and become not writable until INITACK has been cleared. Clear INITACK by clearing
INITREQ in SLCC1. After INITACK is cleared, the SLIC module proceeds to SLIC DISABLED mode (see
Figure 12-2) in which the other SLIC register bits are writable and can be configured to the desired SLIC
operating mode. INITACK is a read-only bit.
0 Normal operation
1 SLIC module is in reset state
0
SLCF
SLIC Interrupt Flag — The SLCF interrupt flag indicates if a SLIC module interrupt is pending. If set, the SLCSV
is then used to determine what interrupt is pending. This flag is cleared by writing a 1 to the bit. If additional
interrupt sources are pending, the bit will be automatically set to 1 again by the SLIC.
0 No SLIC interrupt pending
1 SLIC interrupt pending
1 _{SLCACT may not be clear during all idle times of the bus. For example, if IMSG was used to ignore the data interrupts of an}
extended message frame, SLCACT will remain set until another LIN message is received and either the RX Message Buffer
Full Checksum OK (SLCSV = 0x10) or the TX Message Buffer Empty Checksum Transmitted (SLCSV = 0x08) interrupt
sources are asserted and cleared. When clear, SLCACT always indicates times when the SLIC module is not active, but it is
possible for the SLIC module to be not active with SLCACT set. SLCACT has no meaning in BTM mode.
12.3.5 SLIC State Vector Register (SLCSV)
SLIC state vector register (SLCSV) is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a LIN protocol. It provides an index offset that is directly
related to the LIN module’s current state, which can be used with a user supplied jump table to rapidly
enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state
machine in software.
MC9S08EL32 Series and MC9S08SL16 Series Data Sheet, Rev. 3
Freescale Semiconductor
197