FMS9884A Datasheet, PDF (9/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

FMS9884A
PRODUCT SPECIFICATION
Insufficient clamping can cause brightness changes at the top
of the image and slow recovery from large changes in Aver-
age Picture Level (APL). Recommended value of CD is
0x10 to 0x20 for most standard video sources.
Analog-to-Digital Converter
Figure 2 is a block diagram of the ADC core with gain and
offset functions. G_7-0, OS_5-0, RGB_IN and PD_7-0 generically
refer to the gain and offset register values, analog input and
parallel data output of any RGB channel.
Core of the ADC block is a high speed A/D encoder with dif-
ferential inputs. Within the A/D converter core are the fol-
lowing elements:
1. Differential track and hold.
2. Differential analog-to-digital converter.
Setting the gain register value G_7-0 (GR_7-0, GG_7-0, GB_7-0),
establishes the gain D/A converter voltage which is the A/D
reference voltage. Increasing video gain reduces the contrast
of the picture since the number of output codes is reduced.
Conversion range is defined by the gain setting according to
Table 1.
Table 1. Gain Calibration
G_7-0
Conversion Range (mV)
0
500
66_h
700
FF_h
1000
A/D Converter sensitivity is:
S = ^2----5---5- • -----------2---5---5----------- LSB ⁄ mV
500 255 + G_{7 – 0}
Offset is set through the Single-Ended to Differential Amplifier
which translates the ground referenced input to a differential
voltage centered around A/D common mode bias voltage.
The 6-bit Offset D/A converter injects a current into R_LEVEL
with two components:
1. I_BIAS to establish the A/D common mode voltage.
2. I_OFFSET to set the offset from the common mode level.
Voltage offset from the common mode voltage at the invert-
ing input of the Track and Hold is:
V_OS
=
( OS_5–0
– 31) •
-2---5---5----+-----G----⁷---^–--⁰---
255
•
5----0---0-
255
D/A converter gain tracks A/D gain with 1 LSB of offset cor-
responding to 1 LSB of gain. Increasing OSR_5-0, OSG_5-0, or
OSB_5-0 reduces brightness in the selected channel. Data out-
put from the A/D converter is:
D_7–0 = S • V_IN – ( OS_5–0 – 31 )
Impact of the offset values OSR_5-0, OSG_5-0, and OSB_5-0 is
shown in Table 2.
Table 2. Offset Calibration
OS_5-0
0
1F_h
3F_h
Output Offset (decimal)
+31
0
-32
Sampling Clock PHASE Adjustment
Picture quality is strongly impacted by the PHASE_4-0 value.
If PHASE is not set correctly, any section of an image con-
sisting of vertical lines may exhibit tearing.
Gain
G_7-0
Register
V_REF
D/A
Offset
Register
OS_5-0
Current
D/A
RGB_IN
I_BIAS + I_OFFSET
A/D Core
V_OS
R_LEVEL
Track &
+ _Hold
-
A/D
SCK
Figure 2. A/D Converter Architecture
REV. 1.2.2 12/7/01
D_7-0
9