FMS9884A Datasheet, PDF (17/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

FMS9884A
PRODUCT SPECIFICATION
Table 4. VCO Frequency Bands
FVCO_2-0 Frequency Range (MHz) KVCO (MHz/V)
00
20–90
60
01
10
80–120
90
11
110–175
100
Table 5. Charge Pump Current Levels
IPUMP_2-0
000
001
010
011
100
101
110
111
Current (µA)
50
100
150
250
350
500
750
1500
Setting SPHASE_4-0 selects the sampling phase of SCK rela-
tive to PXCK in 32 steps of 11.25°. Phase of the output data,
DCK and DCK is slaved to the SCK phase.
Clock jitter is less than 5% of pixel period in all operating
modes. At lower frequencies below 40MHz, the jitter rises
but can be reduced by over-sampling at a 2X clock rate. Data
should be read out of one port using the dual port mode. See
Performance section for jitter specifications and plots.
COAST
COAST = H disables PLL lock to HSIN, while the VCO
frequency is retained. VCO frequency remains stable over
several lines without updates from HSIN. COAST can be
connected directly to the vertical sync signal or supplied by
the graphics controller.
Operation of COAST is depicted in Figure 23. HSOUT
polarity is always positive. When COAST = L, HSOUT
tracks HSIN (shown with postive polarity in Figure 23):
1. HSOUT rising edge tracks HSIN delayed by a few pixels.
2. HSOUT falling edge tracks the trailing edge of HSIN
with no delay.
When COAST = H, the PLL flywheels, disregarding the
incoming HSIN references, while the HSOUT waveform
depends upon the state of HSIN.
1. If HSIN = H:
a.) HSOUT rising edge remains locked to the PLL.
b.) HSOUT trailing edge falls after 50% of the HSOUT
period has expired.
2. HSIN transitions:
a.) HSOUT rising edge remains locked to the PLL.
b.) HSOUT falling edge is terminated by the trailing
edge of HSIN.
3. If HSIN = L, then HSOUT = L
Timing Generator
Timing and Control logic generates:
1. Internal sampling clock, SCK.
2. Output data clocks, DCK and DCK.
3. Output horizontal sync, HS_OUT.
4. Internal clamp pulse, ICLAMP.
With HSPOL set correctly, ICLAMP delay follows the trail-
ing edge of horizontal sync in (HSIN). Delay is set by the
CD register. Width of ICLAMP is set by the CW register.
Range of CD and CW values is 1–255 pixels.
HSIN
COAST
Trailing edge terminates HSOUT
HSOUT
50% Timeout
Figure 23.
REV. 1.2.2 12/7/01
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