FMS9884A Datasheet, PDF (10/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
PXCK/XCK
PHASE
FMS9884A
SCK
RINGINBIN
DCK
RGBn
D_7-0
Figure 3. Internal Sampling Clock, SCK Timing
Figure 3 shows how an analog input, R_ING_INB_IN is sampled
by the rising edge of SCK after a delay PHASE from the ris-
ing edge of either PXCK or XCK. SCK can be delayed up to
32 steps in 11.25° increments by adjusting the register value,
PHASE_4-0.
Output data, DCK and DCK are delayed in tandem with
SCK relative to PXCK or XCK. There is a 5-5¹/₂ clock
latency between the data sample RGB_n and the correspond-
ing data out D_7-0.
Ideally, incoming pixels would be trapezoidal with fast rise-
times and the sampling edge of the A/D clock, SCK would
be positioned along the level section of the incoming pixel
waveform as shown in Figure 4. There is a narrow zone of
uncertainly where sampling during pixel rise time would
cause an error in the value of the A/D data output, D_7-0,
which is shown as a value, 0-255.
Zones of Uncertainty
R_IN, G_IN, B_IN
SCK
D_7-0
Zones of Serendipity
R_IN, G_IN, B_IN
SCK
D_7-0
Figure 5. Acceptable Pixel Sampling
Referring to Figure 6, when the sample clock, SCK has some
jitter, if the sampling edge occurs anywhere within the zone
of uncertainty where the pixel rise time is steep, there will be
amplitude modulation of the digitized data, D_7-0, due to the
sampling clock jitter. To avoid corruption of the image, set-
ting the value PHASE_7-0 is critical. PHASE_4-0 should be
trimmed to position the sampling edge of SCK within the
zone of serendipity.
R_IN, G_IN, B_IN
Zones of Uncertainty
Figure 4. Ideal Pixel Sampling
In practice, high-resolution pixels have long rise-times. As
shown in Figure 5, there are narrow zones of serendipity
when the pixel amplitude is level. Samples are valid in these
zones.
SCK
D_7-0
Figure 6. Improper Pixel Sampling
Voltage References
An on-chip voltage reference is generated from a bandgap
source. V_REFOUT is the buffered output of this source that
can be connected to V_REFIN to supply a voltage reference
that is common to the three converter channels.
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REV. 1.2.2 12/7/01