FMS9884A Datasheet, PDF (2/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
FMS9884A
Architectural Overview
Three separate digitizer channels are controlled by common
timing signals derived from the Timing Generator. A/D clock
signals can be derived from either a PLL or an external clock
XCK. With the PLL selected, A/D clocks track the incoming
horizontal sync signal connected to the HSIN input. Setup is
controlled by registers that are accessible through the serial
interface.
Conversion Channels
Typical RGB graphics signals, R_IN, G_IN, B_IN are ground ref-
erenced with 700mV amplitude. If a sync signal is embedded
then the usual format is sync on green with the sync tip at
ground, the black level elevated to 300mV and peak green at
1000mV.
AC coupled video signals must be level shifted to establish
the lower level of the conversion range by clamping to the
black level of the back porch (see Figure 1). Clamp pulses
are derived from internal Timing and Control logic or from
the external CLAMP input.
Output Data Configuration
Output data number format for each channel is binary: 00 cor-
responds to the lowest input; FF corresponds to the highest
input. Data can be released in either of two timing formats:
1. Single 8-bit port at pixel rates up to 175Ms/s.
2. Dual 8-bit ports, each running at half the conversion
rate. Maximum rate is 88Ms/s per port. Data streams
may be parallel or interleaved.
Timing and Control
Timing and Control logic encompasses the Timing Generator,
PLL and Serial Interface.
Timing Generator
All internal clock and synchronization signals are generated
by the Timing Generator. Master Clock source is either the
PLL or the external clock input, XCK. Bit XCKSEL selects
the Master Clock source. Two clocks are generated.
Sampling clock, SCK is supplied to all three A/D converters.
Phase of SCK can be adjusted in 32 11.25 degree phase
increments using the 5-bit PHASE register.
R_IN, G_IN, B_IN
ICLAMP
Figure 1. Clamping to the back-porch
Gain and Offset
Gain and Offset registers serve two functions: adjustment of
contrast and brightness by setting RGB values in tandem;
matching the gain and offsets between channels, by setting
RGB values individually to obtain the same output levels.
A/D conversion range can be matched to the amplitude of the
incoming video signal by programming Gain Registers GR,
GG and GB, which vary sensitivity (LSB/volt) over a 2:1
range. Incoming video signal amplitudes varying from 0.5 to
1.0 volt can be accommodated.
Input offset voltage of each converter is programmable in 1
LSB steps through the 6-bit OSR, OSG and OSB registers.
Range of adjustment is equivalent to –31 to +32 LSB.
A/D Converter
Each A/D converter digitizes the analog input into 8-bit data
words. Latency is 5–6¹/₂ clock cycles, depending upon the
data out format.
V_REFIN is the source of reference voltage for the three A/D
converters. V_REFIN can be connected to either the internal
bandgap voltage, V_REFOUT or an external voltage.
DCK is the output data clock. DCK and DCK are supplied as
outputs for synchronizing data transfer from the digitizer
outputs.
Horizontal sync applied to the input, HS_IN is propagated by
the Timing and Control to the HS_OUT output with a delay
that aligns leading and trailing edges with the output data.
Phase Locked Loop
With a horizontal sync signal connected to the HSIN input
pin, the PLL generates a high frequency internal clock signal,
PXCK that is fed to the Timing and Control logic. Frequency
of PXCK is set by the register programmable PLL divide
ratio, PLLN.
COAST is an input that disables the PLL lock to the horizontal
sync input, HSIN. If HSIN is to be disregarded for a period
such as the vertical sync interval, COAST allows the VCO
frequency to be maintained. Omission of horizontal sync
pulses during the vertical interval can cause tearing at the top
of a picture, if COAST is not used.
Two pixels per clock mode is set by programming the PLL
to half the pixel rate. By toggling the INVCK pin between
frames, even and odd pixels can be read on alternate frames.
Serial Interface
Registers are accessed through an I²C/SMBus compatible
serial port. Four serial addresses are pin selectable.
2
REV. 1.2.2 12/7/01