FMS9884A Datasheet, PDF (15/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

FMS9884A
PRODUCT SPECIFICATION
RGBIN P0 P1 P2 P3 P4 P5 P6 P7
HSIN
PXCK
HS
SCK
6 PIPE DELAY
DATACK
DA_7-0
DB_7-0
HSOUT
D0
D4
D2
D6
Figure 20. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Even Pixels)
RGBIN
HSIN
PXCK
HS
SCK
P0 P1 P2 P3 P4 P5 P6 P7
6.5 PIPE DELAY
DATACK
DA_7-0
DB_7-0
HSOUT
D1
D5
D3
D7
Figure 21. Dual Port Mode, Parallel Outputs, Alternate Pixel Sampling, (Odd Pixels)
Timing and Control
Timing and Control logic encompasses the PLL, Timing
Generator and Sync Stripper.
Phase Locked Loop
Two clock types originate in the PLL:
1. Data clocks DCK and DCK.
2. Internal sampling clock SCK.
DCK and DCK are used to strobe data from the FMS9884A
to following digital circuits. SCK is the ADC sample clock
which has adjustable phase controlled through the PHASE
register. DCK and DCK are phase aligned with SCK.
Reference for the PLL is the horizontal sync input, HSIN
with polarity selected by the HSPOL bit.
Frequency of the HS_IN input is multiplied by the value PLLN
+ 1 derived from the PLLN_11-4 and PLLN_3-0 registers. PLLN
+ 1 should equal the number of pixels per horizontal line
including active and blanked sections. Typically blanking is
20–30% of active pixels. Divide ratios from 2–4095 are
supported. SCK, DCK and DCK run at a rate PLLN + 1
times the HS_IN frequency.
REV. 1.2.2 12/7/01
The PLL consists of a phase comparator, charge pump VCO
and ÷N counter, with the charge pump connected through the
LPF pin to an external filter. These elements must be pro-
grammed to match the incoming video source to be captured.
Values of IPUMP and FVCO for Standard VESA timing
parameters are shown in Table 3. Timing of many computer
video outputs does not comply with VESA recommendations.
PLLN should be optimized to avoid vertical noise bars on the
displayed image.
Modes marked 2X are 2X-oversampled modes where the
number of samples per horizontal line is doubled. To select
this mode, the Phase-locked Loop Divide Ratio value must
changed from PLL_1x to:
PLL_2x = 2 • (PLL_1x + 1) – 1
Values of IPUMP and FVCO are set through the PLL
Configuration Register (0x0C). Recommended external filter
components are shown in Figure 22. RF Quality ±10%
ceramic capacitors with X7R dielectrc are recommended.
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