FMS9884A Datasheet, PDF (24/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
J1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SVGA
RED
GREEN
BLUE
C7
.047µF
R3
HS
75
VSIN
75 R4
SDA
SCL
R10 150
R11 150
C1
.047µF
C4
.047µF R1
75
R5
1K
R6
1K
R8
1.8K
C2
0.18µF
R2
1.5K
R7
1.8K
VDD
R9
10K
VDDP
VDDA
C6
0.018µF
U1
AD9884
33
34
43
48
50
7
15
22
27
28
40
41
44
45
29
30
31
32
14
1
2
3
36
37
38
46
127
PVD
PVD
PVD
PVD
PVD
RIN
GIN
BIN
CLKINV
CLAMP
HSIN
COAST
CKEXT
FILT
SDA
SCL
A0
A1
ACSIN
NC1
NC2
NC3
NC4
NC5
NC6
NC7
REFIN
115
DATACK
116 _DATACK
117 _HSOUT
125 _PWRDN
126
REFOUT
C19
0.1µF
FMS9884A
VDDO
DB _B7
DB _B6
DB _B5
DB _B4
DB _B3
DB _B2
D B_B1
DB _B0
DB _A7
DB _A6
DB _A5
DB _A4
DB _A3
DB _A2
DB _A1
DB _A0
DG_B7
DG_B6
DG_B5
DG_B4
DG_B3
DG_B2
DG_B1
DG_B0
DG_A7
DG_A6
DG_A5
DG_A4
DG_A3
DG_A2
DG_A1
DG_A0
DR_B7
DR_B6
DR_B5
DR_B4
DR_B3
DR_B2
DR_B1
DR_B0
DR_A7
DR_A6
DR_A5
DR_A4
DR_A3
DR_A2
DR_A1
DR_A0
DCSOUT
55
56
57
58
59
60
61
62
65 BA7
66 BA6
67 BA5
68 BA4
69 BA3
70 BA2
71 BA1
72 BA0
75
76
77
78
79
80
81
82
85 GA7
86 GA6
87 GA5
88 GA4
89 GA3
90 GA2
91 GA1
92 GA0
95
96
97
98
99
100
101
102
105 RA7
106 RA6
107 RA5
108 RA4
109 RA3
110 RA2
111 RA1
112 RA0
118
BA [ 7..0]
GA[7..0]
RA[7..0]
DCK
HSOUT
VSOUT
Figure 28. Schematic, VGA Digitizer, Single-Port Outputs
VGA Source with Dual Ported Outputs
Shown in Figure 29 is a more complex implementation of a
video digitizer. Incoming RGB video has sync-on-green.
Output data is dual ported. COAST is shown to free wheel
the PLL when horizontal sync is inactive or 2H pulse are
present.
RGB inputs signals are AC coupled to the FMS9884A RGB
inputs with the green input connected to the Sync Separator
input, CVIN.
Output data is three channel dual port data with a maximum
rate of 70Ms/s per port. Port A data is synchronzed to the
negative edge of DCK. Port B data transitions on:
1. Positive edge of DCK in the Parallel Data Out Mode.
2. Negative edge of DCK in the Interleaved Data Out
Mode.
DCK and DCK clocks should be timed to strobe data that is
valid between transitions.
Composite Sync from the Sync Stripper output CSOUT is
supplied to the HSYNC input as a reference for the internal
PLL. CSSOUT contains horizontal and vertical sync signals
that can be extracted by subsequent Sync processing logic. If
the vertical sync pulse omits horizontal sync or if serrations
or equalizing pulses are present, then the sync processing
logic should emit a COAST signal to disengage the PLL
from the HSYNC input during the Vertical Sync interval.
Vertical and horizontal sync waveforms within CSSOUT
signal frame the active video area.
24
REV. 1.2.2 12/7/01