FMS9884A Datasheet, PDF (23/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

FMS9884A
PRODUCT SPECIFICATION
System Performance Characteristics (continued)
Parameter
Thermal
θ_JC Resistance, junction-to-case
θ_JA Resistance, junction-to-ambient
Notes:
1. Calibrated to 700 mV input.
2. Percentage of Full Scale (uncalibrated).
7
Conditions Min. Typ.
8.4
35
6
5
4
3
2
1
0
0 20 40 60 80 100 120 140 160 180 200
Pixel Clock (MHz)
Max.
Unit
°C/W
°C/W
Figure 27. Pixel Clock Jitter vs. Frequency
Applications Information
Two applications circuits are reviewed:
1. AC coupled digitizer with clamp.
2. AC coupled digitizer with dual ported outputs and sync
stripping.
To minimize component count, use of the following on-chip
circuits is recommended:
1. ADC sampling clock.
2. Clamp.
3. Voltage reference
4. Dual ported data outputs
Optimum PLL Configuration Register (address 0x0C) set-
tings for typical graphics modes are listed in Table 3. Unless
otherwise indicated, all modes are compliant with VESA
specifications. For unlisted modes, values should be adjusted
to optimize performance.
By adjusting the values in the gain (GR, GG, GB) and offset
(OSR, OSG, OSB) registers, the input conversion range can
be matched to the incoming analog signals.
To use the FMS9884A in applications where the PLL clock
frequency will exceed 140 MHz, the PLL power supply
voltage must be 3.4 V min. For applications up to and
including 140 MHz, the PLL supply can be 3.0 V min.
AC Coupled Digitizer
Shown in Figure 28 is an implementation of a video digitizer
with AC coupled RGB inputs. Horizontal sync input, HS is
passed through a voltage divider which attenuates the 5.0 V
logic HIGH excursion to the 3.3 V HIGH input level of the
FMS9884A. Vertical sync is also attenuated to make the
VSOUT level compatible with 3.3 V pixel processing fol-
lowing the FMS9884A.
Output data is three channel port A data only with a maxi-
mum rate of 175Ms/s 24-bit pixels. Data is clocked out on
the negative edge of DCK. HSOUT defines the active video
along a line, while incoming vertical sync, VSIN is propa-
gated as VSOUT to the output data to synchronize handling
of digitized frames of output data.
Control is through the serial port with 150Ω resistors
inserted to allow interfacing with 5V logic. If the serial bus is
operates with 3.3V levels, these resistors are unnecessary.
REV. 1.2.2 12/7/01
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