FMS9884A Datasheet, PDF (26/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

PRODUCT SPECIFICATION
7. Bypass the reference with a 0.1µF capacitor to ground.
R,G, B INPUT
L1
BEAD
C1
47nF
R_IN, G_IN, B_IN
R1
C2
75
10pF
Figure 30. RGB Input Filter Options
Digital I/O
Recommendations:
1. Route digital I/O signals clear of analog inputs.
2. Terminate clock lines to reduce reflections. Treat clock
lines as transmission lines.
3. Scale the HSIN input to 3.3V, using a resistor network
or a series 1 kΩ resistor.
4. Limit Serial Port inputs SDA and SDL with 150Ω
resistors connected directly to the pins.
FMS9884A
5. If necessary terminate the HSIN input with 330/220Ω.
6. If necessary, to reduce reflections, EMI or spikes add a
50–200Ω resistor at each data output pin.
7. To minimize noise within the FMS9884A, restrict the
capacitive load at the digital outputs to < 10pF.
Power and Ground
A schematic of the recommended power distribution is
shown in Figure 31. Note that:
1. Analog and digital circuits are layed out over a common
solid ground plane.
2. Each FMS9884A pin is decoupled with a 0.1µF capacitor.
3. A group of pins may be de-coupled through a common
capacitor if no pin is more than 5 mm from the capacitor.
4. A separate regulated supply is used for the phase-locked
loop power supply, V_DDP.
5. Capacitors are attached to each PLL pin or pin-pair.
Pins 33, 34
C2
0.01µF
L1
VPLL BEAD
U3
RC1117-3.3
2 _OUT
4 _OUT
IN ³
ADJ/GND
1
C1
0.1µF
Pin 43
C3
0.1µF
VADC Pins
VDD Pins
Pin 48
C4
0.01µF
Pin 50
C5
0.1µF
+ C6
10 µF
L2
BEAD
U2
RC1117-3.3
2 _OUT
4 _OUT
3
IN
ADJ/GND
1
C7
0.1µF
C10 C11 C12 C13 C14 C15 C16 C17
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
+ C26
10 µF
C18 C19 C20 C21 C22 C23 C24
0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF 0.1µF
L3
BEAD
U3
RC1117-3.3
2 _OUT
4 _OUT
ADJ/GND ^IN
3
+ _C25
1
10µF
C9
0.1µF
Power Input
+ C8
10µF
Figure 31. Recommended Power Distribution
26
REV. 1.2.2 12/7/01