FMS9884A Datasheet, PDF (19/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

FMS9884A
PRODUCT SPECIFICATION
There are five steps within an I²C/SMBus cycle:
1. Start signal
2. Slave address byte
3. Pointer register address byte
4. Data byte to read or write
5. Stop signal
When the Serial Bus interface is inactive, SCL = H and SDA
= H. Communications are initiated by sending a start signal
(Figure 24, left waveform) that is a HIGH-to-LOW transition
on SDA while SCL is HIGH. A start signal alerts all slaved
devices that a data transfer sequence is imminent.
As shown in Figure 26, after a start signal, the first eight bits of
data comprise a seven bit slave address followed a single
R/W bit (Read = H, Write = L) to set the direction of data
transfer: read from; or write to the slave device. If the trans-
mitted slave address matches the address of the FMS9884A
which set by the state of the ADD pin, the FMS9884A
acknowledges by pulling SDA LOW on the 9th SCL pulse
(see Figure 26). If the addresses do not match or the register
being accessed is 0x0F, the FMS9884A does not
acknowledge.
For each byte of data read or written, the MSB is the first bit
of the sequence.
Data Transfer via Serial Interface
If a slave device, such as the FMS9884A does not acknowl-
edge the master device during a write sequence, SDA
remains HIGH so the master can generate a stop signal. Dur-
ing a read sequence, if the master device does not acknowl-
edge by bringing SDA = L, the FMS9884A interprets SDA =
H as “end of data.” SDA remains HIGH so the master can
generate a stop signal (Figure 24, right waveform).
To write data to a specific FMS9884A control register, three
bytes are sent:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write to the control register indexed by the pointer.
After each byte is written, the pointer auto-increments to
allow multiple data byte transfers within one write cycle.
Data is read from the control registers of the FMS9884A in a
similar manner, except that two data transfer operations are
required:
1. Write the slave address byte with bit R/W = L.
2. Write the pointer byte.
3. Write the slave address byte with bit R/W = H
4. Read the control register indexed by the pointer.
After each byte is read, the pointer auto-increments to allow
multiple data byte transfers within one read cycle.
Preceding each slave write, there must be a start cycle.
Following the pointer byte there should be a stop cycle.
After the last read, there must be a stop cycle comprising
a LOW-to-HIGH transition of SDA while SCL is HIGH.
(see Figure 24, right waveform)
A repeated start signal occurs when the master device driving
the serial interface generates a start signal without first gener-
ating a stop signal to terminate the current communication.
This is used to change the mode of communication (read,
write) between the slave and master without releasing the
serial interface lines.
Serial Interface Read/Write Examples
Examples below show how serial bus cycles can be linked
together for multiple register read and write access cycles.
For sequential register accesses, each ACK handshake ini-
tiates further SCL clock cycles from the master to transfer
the next data byte.
Write to one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Stop signal
Write to four consecutive registers
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte
4. Data byte to base address
5. Data byte to (base address + 1)
6. Data byte to (base address + 2)
7. Data byte to (base address + 3)
8. Stop signal
Read from one register
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Stop signal
Read from four registers
1. Start signal
2. Slave Address byte (R/W bit = LOW)
3. Pointer byte (= base address)
4. Stop signal (optional)
5. Start signal
6. Slave Address byte (R/W bit = HIGH)
7. Data byte from base address
8. Data byte from (base address + 1)
9. Data byte from (base address + 2)
10. Data byte from (base address + 3)
11. Stop signal
REV. 1.2.2 12/7/01
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