FMS9884A Datasheet, PDF (5/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

FMS9884A
PRODUCT SPECIFICATION
Pin Descriptions
Pin Name Pin No. Type/Value Pin Function Description
Converter Channels
R_IN, G_IN, B_IN 7, 15, 22
DRA_7-0
105–112
Input
Output
Analog Inputs.
Red Channel Port A Data Output. Full rate/half rate, interleaved/
parallel data depending upon selected mode.
DRB_7-0
95–102
Output
Red Channel Port B Data Output. Active for dual port mode only with
interleaved/parallel outputs. High impedance when inactive.
DGA_7-0
85–92
DGB_7-0
75–82
DBA_7-0
65–72
DBB_7-0
55–62
Timing Generator
Output
Output
Output
Output
Green Channel Port A Data Output. See red channel port A.
Green Channel Port B Data Output. See red channel port B.
Blue Channel Port A Data Output. See red channel port A.
Blue Channel Port B Data Output. See red channel port B.
CLAMP
28
Input
External Clamp Input.
INVSCK
27
Input
Invert Sampling Clock. Inverts SCK, the internal clock sampling the
analog inputs. Supports Alternate Pixel Sampling mode for capture
pixel rates up to 350Ms/s.
XCK
44
Input
External Clock input. Enabled if register bit, XCKSEL = H. Replaces
PXCK clock generated by PLL. If unused, connect to ground through a
10kΩ resistor.
DCK
115
Output Output Data Clock. Clock for strobing output data to external logic.
DCK
116
Output Output Data Clock Inverted. Inverted clock for strobing output data to
external logic.
HSOUT
117
Output Horizontal Sync Output. Reconstructed HSYNC delayed by
FMS9884A latency and synchronized with DCK. Leading edge is
synchronized to start of data output. Polarity is always active HIGH.
Phase Locked Loop
HSIN
40
Schmitt Horizontal Sync input. Schmitt trigger threshold is 1.5V. A 5V source
should be clamped at 3.3V or current limited to prevent overdriving
ESD protection diodes.
COAST
41
Input
PLL Coast. Maintain frequency of PLL output clock PXCK,
disregarding HSIN. If horizontal sync is missing during the vertical sync
interval, PXCK clock frequency can be maintained by asserting
COAST.
LPF
45
Passive PLL Low Pass Filter. Connect recommended PLL filter to LPF pin.
(see Figure 19.)
Sync Stripper
ACS_IN
14
Analog Composite Sync Input. Input to sync stripper with 150mV
threshold.
DCS_OUT
118
Control
Digital Composite Sync Output. Output from sync stripper.
SDA
29 Bi-directional Serial Port Data. Bi-directional data.
SCL
30
Input
Serial Port Clock. Clock input.
A₀
31
A₁
32
PWRDN
125
Input
Input
Input
Address bit 0. Lower bit of serial port address.
Address bit 1. Upper bit of serial port address.
Power Down/Output Control. Powers down the FMS9884A and
tri-states the outputs.
REV. 1.2.2 12/7/01
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