FMS9884A Datasheet, PDF(11/29 Page) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

FMS9884A Datasheet, PDF (11/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

◁

FMS9884A

PRODUCT SPECIFICATION

VREFIN, with a nominal voltage of 1.25V, is the source of the

differential reference voltages for each A/D converter.

Reference voltages supplied to the differential inputs of the

comparators in the A/D converters are derived from VREFIN.

Digital Data Outputs

Input horizontal sync, HSIN and outgoing data, D[7..0] are

resynchronized to the delayed sample clock, SCK. Output

timing characteristics are deï¬ned in Figure 7. Latency of the

ï¬rst pixel, N varies according to the mode:

1. Single or dual output port.

2. Interleaved or parallel output data.

3. 1-pixel or 2-pixel.

Levels are 3.3 volt CMOS with the output supply variable

between 2.5 and 3.3 V. PWRDN = L sets the outputs

high-impedance. PWRDN = H enables the outputs.

HSIN

PXCK/XCK

PHASE

SCK

RGBIN

DCK

D[7..0]

tDH

tDO

HSOUT

Figure 7. Output Timing

Figures 13 through 21 depict data output timing relative to

the sampling clock and inputs for all modes. Timing is refer-

enced to the leading edge of HSIN when the ï¬rst sample is

taken at the rising edge of SCK. Status of register bit OUT-

PHASE, determines if even samples are directed the A-port

and odd samples are directed to the B-port; or vice versa.

Note the timing of the HSOUT waveform:

1. HSOUT is always active HIGH.

2. Only the leading edge of HSOUT is active or selected by

the HSPOL register bit.

3. HSOUT is aligned with DCK.

4. Trailing edge is linked to HSIN.

5. If HSIN does not terminate before mid-line, HSOUT is

forced low. A 50% duty cycle indicates that HSPOL is

incorrectly set.

HS is the internal sync pulse generated from HSYNC. SCK

is the internal A/D converter sampling clock.

Output data transitions are synchronized with the falling

edge of DCK. Output data should be strobed on the rising

edge of DCK. A 5 to 6.5 clock cycle delay must be ï¬ushed

before valid data is available.

Alternate Pixel Sampling Mode

A logic H on the CKINV pin inverts the sampling phase of

SCK. In the Alternate Pixel Sampling Mode:

1. PLL is run at half rate. SCK, DCK and DCK are half rate.

2. CKINV is toggled between frames. (see Figure 18)

REV. 1.2.2 12/7/01

▷