FMS9884A Datasheet, PDF (7/29 Pages) Fairchild Semiconductor – 3x8-Bit, 108/140/175 Ms/s Triple Video A/D Converter with Clamps

FMS9884A
PRODUCT SPECIFICATION
Name
PHASE_7-0
PLLCTRL
CONFIG2
Address
0B
0C
0D
0E
0F
Function
Sampling clock phase. PHASE_4-0 stored in upper
register bits 7-3. PHASE sets the sampling clock phase in
11.25° increments. Default value is decimal 16.
PHASE_4–0 X X X
PLL Control
Configuration
Reserved
Reserved
Default (hex)
80
24
00
0X
00
Register Definitions
Configuration Register 1 (0A)
Bit no.
0
1
2
3
4
5
6
7
Name
XCKSEL
XCLAMPOL
XCLAMP
COASTPOL
HSPOL
PARALLEL
DEMUX
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
External Clock Select. Select internal clock source.
0: Internal PLL
1: XCK input.
External Clamp Polarity. Select clamp polarity.
0: Active L.
1: Active H.
External Clamp Select. Select clamp source.
0: Internally generated by PLL referenced to HSIN.
1: External CLAMP input.
Coast Polarity. Select COAST input polarity.
0: Active L.
1: Active H.
HSIN Polarity. Select horizontal sync input polarity. PLL is locked to selected
edge:
0: Falling edge.
1: Rising edge.
Output Data Format. Select format of data outputs.
0: Interleaved. DCK rising edge strobes port A data. DCK rising edge strobes
port B data.
1: Parallel. Rising edge of DCK strobes port A and port B data.
Output Data Porting. Data released at full rate through one port or through
two half-rate ports.
0: Single 8-bit port.
1: Dual 8-bit ports.
PLL Configuration Register (0C)
Bit no. Name Type Description
1-0
—
4-2
IPUMP_2-0 R/W Charge Pump Current. Selects Charge Pump current (µA).
(see Table 5. Charge Pump Current Codes)
000: 50
001: 100
010: 150
011: 250
100: 350
101: 500
110: 750
111: 1500
REV. 1.2.2 12/7/01
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