XR28V384IM48-0A Datasheet, PDF (8/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
1.1.2.3.2
Index port address 0x4E & Data port address 0x4F
write (0x4E, 0x67);
write (0x4E, 0x67);
//write entry key (0x67) twice to configuration port
//Enable access to the configuration registers
write (0x4E, 0x23);
//Select the VID_M register
read (0x4F);
//Read the VID_M register
write (0x4E, 0x24);
//Select the VID_L register
read (0x4F);
//Read the VID_L register
write (0x4E, 0x25);
//Select the Clock Select Register
write (0x4F, 0x0);
//Select the input clock frequency 24 MHz
write (0x4E, 0x7);
//Select the LDN register
write (0x4F, 0x0);
//Select the UART Channel A
write (0x4E, 0x60);
write (0x4F, 0x3);
//Set the UART Channel A base address high byte as 0x3
write (0x4E, 0x61);
write (0x4F, 0xF8);
//Set the UART Channel A base address low byte as 0xF8
write (0x4E, 0xF6);
//Select the FIFO Mode Select Register of UART Channel A
write (0x4F, 0x0);
//Set the FIFO size 16 bytes,
//RX trigger level 1, 4, 8, 14 and no delay for THR empty interrupt
write (0x4E, 0x30);
write (0x4F, 0x1);
//Enable the UART Channel A
write (0x4E, 0xAA);
//Disable access to the configuration registers
1.2 LPC Bus Interface
The LPC bus interface has a 4-bit multiplexed address/data bus, 1 reset signal, 1 clock and 1 control signal. It
also has one interrupt signal. The V384 implements the following signals of the LPC bus.
■ LFRAME# is used by the host to start or stop transfers.
■ LCLK is a clock used for synchronization.
■ PCIRST# is an active low reset signal.
■ LAD[3:0] signal lines communicate device address, control (read, write, wait and transfer type), and data
information over the LPC bus between a host and a peripheral.
■ Interrupt requests are issued through SERIRQ.
1.2.1 Serial IRQ
The V384 supports a serial IRQ scheme specified in specification for Serialized IRQ support for PCI system
Rev6.0 which allows SERIRQ pin to be shared with multiple devices. The SERIRQ signal is tri-stated when
idle. The SERIRQ is divided into 3 types of time slots known as Frames: Start frame, IRQ frame, and Stop
frame. The SERIRQ uses LCLK for timing. There are two modes of operation for SERIRQ signal: Quiet mode
and Continuous mode. These two modes are discussed in further detail in ’Section 1.2.1.1, Start Frame’.
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