XR28V384IM48-0A Datasheet, PDF (10/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
1.2.1.3 Stop Frame
After all IRQ/Data Frames have been completed, the host controller will terminate SERIRQ by a Stop frame.
Only the host controller can initiate the Stop frame by driving SERIRQ low for 2 or 3 clocks. If the Stop Frame
is low for 2 clocks, the next SERIRQ cycle will be the Quiet mode whereas if it is low for 3 clocks, the next
SERIRQ cycle will be the Continuous mode.
1.3 Watchdog Timer (WDT)
The WDT is typically used in a system to initiate any of the several types of corrective action, including
processor reset, power cycling, fail-safe activation etc. The Watchdog timer of V384 is an 8 bit counter
controlled by six registers. See ”Section 2.1.2.2, Watchdog Timer Registers (LDN = 0x08)” on page 26.
WDTOUT# idles HIGH and will transition LOW when a time out occurs. The V384 provides three time
intervals: 10 ms, 1s and 1 minute allowing for timeouts ranging from approximately 2.5 seconds to more than 4
hours. See ’Section 2.1.2.2.4, WDT Timer Status and Control Register - Read/Write’ to set up time interval.
1.4 UART
1.4.1 External Clock Input (CLKIN)
Along with LCLK, the V384 also needs an external clock for UART data communication. It can support any
clock up to 48MHz. The 24MHz and 48MHz are the standard clock frequencies supported by the V384. See
’Section 2.1.1.5, Clock Select Register - Read/Write’.
1.4.1.1 Programmable Baud Rate Generator
Each UART has its own Baud Rate Generator (BRG) with a prescaler. The prescaler is controlled by Bit[1:0] of
Enhanced Multifunction Register - Read/Write.
Table 5 shows the standard data rates available with a 24 MHz external clock at 16X sampling rate and
internal clock frequency set to 1.8462 MHz. The divisor value can be calculated for DLL/DLM with the following
equation.
divisor (decimal) = (Internal clock frequency ) / (serial data rate x 16)
BAUD Rate
(BPS)
150
300
600
1200
2400
4800
9600
19200
38400
57600
115200
TABLE 5: TYPICAL DATA RATES WITH A 1.8462MHZ INTERNAL CLOCK
DIVISOR FOR 16x DIVISOR FOR 16x
Clock (Decimal) Clock (HEX)
768
300
384
180
192
C0
96
60
48
30
24
18
12
0C
6
06
3
03
2
02
1
01
DLM
PROGRAM
VALUE (HEX)
03
01
00
00
00
00
00
00
00
00
00
DLL
PROGRAM
VALUE (HEX)
00
80
C0
60
30
18
0C
06
03
02
01
ACTUAL
BAUD RATE
150.24
300.48
600.96
1201.92
2403.85
4807.69
9615.39
19230.77
38461.54
57692.31
115384.6
DATA RATE
ERROR (%)
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
0.2
Table 8 lists the different internal clock settings.
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