XR28V384IM48-0A Datasheet, PDF (13/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
1.4.3.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the receive
FIFO of up to 128 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register.
When the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After
the RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data
byte are immediately updated in the LSR bits 2-4.
FIGURE 5. RECEIVER OPERATION IN NON-FIFO MODE
Clock
Receive Data Shift Data Bit
Register (RSR)
Validation
Receive Data Characters
Receive
Data Byte
and Errors
Error
Tags in
LSR bits
4:2
Receive Data
Holding Register
(RHR)
FIGURE 6. RECEIVER OPERATION IN FIFO MODE
RHR Interrupt (ISR bit-2)
RXFIFO1
C lo c k
Up to 128 byte
11-bit width
FIFO
Receive Data
Byte and Errors
Receive Data Shift
Register (RSR)
Data Bit
V a lid a tio n
Receive Data Characters
E xa m p le
: - RX FIFO trigger level selected at 8 bytes
R e ce ive
Data FIFO
FIFO
Trigger=8
RH R Interrupt (ISR bit-2) programm ed for
desired F IF O trigger level.
F IF O is E nabled by FC R bit-0=1
R e ce ive
D a ta
R X F IF O 1
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