XR28V384IM48-0A Datasheet, PDF (14/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
1.4.4 Auto RS-485 Half-Duplex Control
The Auto RS-485 Half-Duplex Control feature changes the behavior of the RTS#/RS485 pin when enabled by
Enhanced Multifunction Register - Read/Write bit-4. If enabled, by default, it de-asserts RTS#/RS485 ouput
following the last stop bit of the last character that has been transmitted. This helps in turning around the
transceiver to receive the remote station’s response. When the host is ready to transmit data packet, it only has
to load data bytes to the transmit FIFO. The transmitter automatically asserts RTS#/RS485 output prior to
sending the data. The polarity of RTS#/RS485 signal can be modified by bit-5 of Enhanced Multifunction
register.
1.4.5 Normal Multidrop (9-bit) Mode
Normal multidrop mode is enabled when bit-7 of Enhanced Multifunction register in the UART Device
Configuration Registers is set to ’1’. In the multidrop (9-bit) mode, the parity bit becomes the address/data bit.
If a data byte is received (9th bit is '0'), it will be loaded into the RX FIFO and the parity error bit will be '0'. If an
address byte is received (9th bit is '1'), it will be loaded into the RX FIFO and the parity error bit will be '1'.
When the address byte has been received, the software will need to examine the byte: If the address matches
its slave address, the receiver will receive the subsequent data; If the address does not match its slave
address, then the receiver will discard the data.
1.4.5.1 Auto Address Detection
Auto Address Detection mode is enabled when bit-6 of Enhanced Multifunction register (0xF0) in UART device
configuration registers set is set to ’1’. The desired slave address will need to be written into the 9-bit mode
slave address register (0xF4) in the UART device configuration registers set. If the received byte is an address
byte that does not match the programmed character in the 9-bit mode slave address register, the receiver will
discard these data. Upon receiving an address byte that matches the 9-bit mode slave address register
character, the receiver will automatically push the address byte into the RX FIFO and set the parity error bit in
the LSR register. The receiver also generates an LSR interrupt if enabled. The receiver will then receive the
subsequent data. If another address byte is received and does not match the programmed 9-bit mode slave
address register value, then the receiver will ignore the data that follows.
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