XR28V384IM48-0A Datasheet, PDF (24/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
Bits [1:0]: Internal clock frequency
The V384 provides an option to select among various internal clock frequency, which is used to generate
different baud values. The value of the internal clock frequency is dependent on external clock provided to the
CLKIN pin and setting of Clock Select Register - Read/Write. Table 8 describes various possible internal
clock frequencies derived from 24MHz/48MHz external clock.
TABLE 8: INTERNAL CLOCK FREQUENCY (MHZ)
BITS[1:0]
EXTERNAL CLOCK = 24MHZ
EXTERNAL CLOCK = 48MHZ
CLKSEL=0X0
CLKSEL=0X1
CLKSEL=0X0
CLKSEL =0X1
00
1.8462
0.9231
3.6923
1.8462
01
18
9
36
18
10
24
12
48
24
11
14
7
28
14
See ’Section 1.4.1.1, Programmable Baud Rate Generator’.
Bit [2]: IR mode TX Delay
x Logic 0 = TX transmits data immedately when changing from RX to TX (default).
x Logic 1 = TX delays 4 character time when changing from RX to TX.
Bit [3]: IR mode RX Delay
x Logic 0 = RX is enabled immediately after TX is idle (default).
x Logic 1 = RX is disabled for 4 character time after TX is idle.
Bit [4]: Enable/Disable Auto RS-485 Half-Duplex Control mode
x Logic 0 = Disable the Auto RS-485 Half-Duplex Control mode (default). The RTS#/RS485 pin can be
controlled by MCR bit-1.
x Logic 1 = Enable the Auto RS-485 Half-Duplex Control mode. The RTS#/RS485 signal polarity is determined
by the bit-5.
Bit [5]: Invert the RTS#/RS485 signal polarity for RS-485 Half-Duplex Control mode
x Logic 0 = RTS#/RS485 signal polarity is HIGH for transmission and LOW for reception (default).
x Logic 1 = RTS#/RS485 signal polarity is inverted (that is, LOW for transmission and HIGH for reception).
Bit [6]: Auto Address Detection
x Logic 0 = All bytes received will be loaded into RX FIFO. See ’Section 1.4.4, Auto RS-485 Half-Duplex
Control’.
x Logic 1 = All bytes received after address byte that matches the given address or broadcast address
(determined by the 9-bit mode slave address register and 9-bit mode slave address mask register) will be
loaded into RX FIFO. See ’Section 1.4.5.1, Auto Address Detection’.
Bit [7]: Enable/Disable the 9-bit Mode
x Logic 0 = Disable the 9-bit mode (default).
x Logic 1 = Enable the 9-bit mode (multi-drop mode).
In the 9-bit mode, the parity bit becomes the address/data bit.See ’Section 1.4.5, Normal Multidrop (9-bit)
Mode’.
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