XR28V384IM48-0A Datasheet, PDF (19/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
2.0 REGISTER DETAILS
The Register map of V384 is primarily divided into two sections:
x Configuration Register set
x UART internal Register set
2.1 Configuration Register
There are two different sets of configuration registers: the Global Control Register set and the Device
Configuration Register set. The Global Control Registers can be used to perform software reset, select clock
input frequency, configure watchdog timer, configuration port selection and read Vendor ID and Device ID. The
Device Configuration Registers configure all 4 UARTs to enable the UART channel, base address, IRQ
channel, internal clock frequency, IR control, 9-bit mode slave address and FIFO mode. The watchdog timer
can also be configured in the Device Configuration Registers set including enable the watchdog timer,
configure base address, IRQ channel, timer count number and monitor the timer status.
x Global Control Registers
The Global Control Register set is the set of registers that are shared among all the devices of V384. Table 6
describes the list of all the Global Control Registers.
TABLE 6: LPC BUS GLOBAL CONTROL REGISTERS
ADDRESS [A7:A0]
REGISTER
READ/WRITE COMMENT
RESET STATE
0x02
Software Reset Register
Read/Write
Bits [7:0] = 0x00
0x07
Logic Device Number Register (LDN)
Read/Write
Bits [7:0] = 0x00
0x20
Device ID MSB Register (DEV_ID_M)
Read-only
Bits [7:0] = 0x03
0x21
Device ID LSB Register (DEV_ID_L)
Read-only
Bits [7:0] = 0x84
0x23
Vendor ID MSB Register (VID_M)
Read-only
Bits [7:0] = 0x13
0x24
Vendor ID LSB Register (VID_L)
Read-only
Bits [7:0] = 0xA8
0x25
Clock Select Register (CLKSEL)
Read/Write
Bits [7:0] = 0x00
0x26
Watchdog Timer Control Register (WDT)
Read/Write
Bits [7:0] = 0x00
0x27
Port Select Register
Read/Write
Bits [7:0] = 0x00
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