XR28V384IM48-0A Datasheet, PDF (6/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
1.0 FUNCTIONAL DESCRIPTIONS
1.1 Power on Strapping Options
At power-on, strapping options for each pin listed in Table 1 result in the register values based upon the pin
state selected. These register values can also be modified by the software.
1.1.1 UART/Watchdog Timer Options
The V384 provides seven pins for power on hardware strapping options to select the settings of the UART
channels and Watchdog Timer.
TABLE 1: UART POWER ON CONFIGURATION
REGISTER VALUES
PIN
NUMBER
PIN NAME
PIN
STATE
ENABLE
(0X30)
BASE
ADDRESS
HIGH
REGISTER
(0X60)
BASE
ADDRESS
LOW
REGISTER
(0X61)
IRQSEL
(0X70)
COMMENT
18
TXD /
1
0x1
PS_2E8_IRQD
0
0x0
0x2
0xE8
0x9
0x0
0x0
0x0
26
TXC /
1
0x1
PS_3E8_IRQC
0
0x0
0x3
0xE8
0x5
0x0
0x0
0x0
34
DTRB# /
1
0x1
PS_2E0_IRQB
0
0x0
36
TXB /
1
0x1
PS_2F8_IRQB
0
0x0
0x2
0xE0
0x0
0x0
0x2
0xF8
0x0
0x0
0x4
0x0
When both pins
are high, the
0x4
base address
will be 0x2F8.
0x0
42
DTRA# /
1
0x1
PS_3E0_IRQA
0
0x0
44
TXA /
1
0x1
PS_3F8_IRQA
0
0x0
0x3
0xE0
0x0
0x0
0x3
0xF8
0x0
0x0
0x3
0x0
When both pins
are high, the
0x3
base address
will be 0x3F8.
0x0
24
DTRC# /
1
0x1
PS_WDT
0
0x0
0x4
0x42
0x0
0x0
0x0
0x0
After power-on, the Enable, Base Address High & Low, IRQSEL registers can be modified by the software.
1.1.2 Configuration Port and Key Selection Options
1.1.2.1 Configuration Port Selection Option
The configuration registers are programmed by the index port and the data port. The port address is
determined by the strap pin RTSA#/PS_CONF_2E/RS485. If an external pull-down resistor is not installed, the
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