XR28V384IM48-0A Datasheet, PDF (29/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

REV. 1.0.0
XR28V384
3.3V QUAD LPC UART WITH 128-BYTE FIFO
TABLE 11: UART INTERNAL REGISTER
OFFSET ^{REG READ/}
ADDRESS _{NAME WRITE}
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3 BIT-2 BIT-1 BIT-0 COMMENT
16C550 Compatible Registers
0x0
RHR RD
Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0x0
THR WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
0x1
IER RD/WR 0
0
0
0
Modem RX Line TX
RX ^{LCR[7] = 0}
Stat. Int. Stat. Empty Data
Enable Int.
Int
Int.
Enable Enable Enable
0x2
ISR RD FIFOs FIFOs
0
Enabled Enabled
0
INT
INT INT INT
Source Source Source Source
Bit-3 Bit-2 Bit-1 Bit-0
0x2
FCR WR RXFIFO RXFIFO
0
0
Trigger Trigger
0
TX
RX FIFOs
FIFO FIFO Enable
Reset Reset
0x3
LCR RD/WR Divisor Set TX Set
Even
Parity Stop Word Word
Enable Break _Parity Parity Enable Bits Length Length
Bit-1 Bit-0
0x4 MCR RD/WR 0
0
0
Internal Enable OP1# RTS# DTR#
Lopback Interrupts/
Output Output
Enable OP2#
Control Control
0x5
LSR RD RX FIFO THR & THR RX Break RX Fram- RX
RX
RX
Global TSR Empty
ing Error Parity Over- Data
Error Empty
Error run Ready
Error
0x6
MSR RD
CD#
RI# DSR# CTS#
Delta Delta Delta Delta
Input Input Input Input
CD#
RI# DSR# CTS#
0x7
SPR RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3 Bit-2 Bit-1 Bit-0
Baud Rate Generator Divisor
0x0
DLL RD/WR Bit-7 Bit-6 Bit-5
Bit-4
0x1
DLM RD/WR Bit-7 Bit-6 Bit-5
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
LCR[7] = 1
Bit-0
2.2.1 UART Internal Register Descriptions
2.2.1.1 Receive Holding Register (RHR) - Read- Only
SEE “RECEIVER” ON PAGE 12.
2.2.1.2
Transmit Holding Register (THR) - Write-Only
SEE “TRANSMITTER” ON PAGE 11.
2.2.1.3 Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
29