XR28V384IM48-0A Datasheet, PDF (32/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
ISR[7:6]: FIFO Enable Status
These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are
enabled.
2.2.1.5
FIFO Control Register (FCR) - Write-Only
This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO trigger levels. The FIFO
mode is defined as follows:
FCR[0]: TX and RX FIFO Enable
x Logic 0 = Disable the transmit and receive FIFO (default).
x Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are
written or they will not be programmed. See FIFO Mode Select Register - Read/Write bit [1:0] for FIFO size
selection.
FCR[1]: RX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
x Logic 0 = No receive FIFO reset (default).
x Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[2]: TX FIFO Reset
This bit is only active when FCR bit-0 is a ‘1’.
x Logic 0 = No transmit FIFO reset (default).
x Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not
cleared or altered). This bit will return to a logic 0 after resetting the FIFO.
FCR[5:3]: Reserved
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