XR28V384IM48-0A Datasheet, PDF (12/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
1.4.2.3
Transmitter Operation in FIFO Mode
The host may fill the transmit FIFO with up to 128 bytes of transmit data. The THR empty flag (LSR bit-5) is set
whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the
FIFO becomes empty. The transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set
when TSR/FIFO becomes empty.
FIGURE 4. TRANSMITTER OPERATION IN FIFO MODE
Transmit
Data Byte
Transmit
FIFO
THR Interrupt (ISR bit-1) when TX
FIFO becomes empty. FIFO is
enabled by FCR bit-0=1
Clock
Transmit Data Shift Register
(TSR)
TXFIFO1
1.4.3 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and up to 128 bytes of FIFO which
includes a byte-wide Receive Holding Register (RHR). The RSR uses the internal sampling clock for timing. It
verifies and validates every bit on the incoming character in the middle of each data bit. On the falling edge of
a start or false start bit, an internal receiver counter starts counting at the clock rate. After 8 clocks the start bit
period should be at the center of the start bit. At this time the start bit is sampled and if it is still a logic 0 it is
validated. Evaluating the start bit in this manner prevents the receiver from assembling a false character. The
rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. If
there were any error(s), they are reported in the LSR register bits 2-4. Upon unloading the receive data byte
from RHR, the receive FIFO pointer is bumped and the error tags are immediately updated to reflect the status
of the data byte in RHR register. RHR can generate a receive data ready interrupt upon receiving a character
or delay until it reaches the FIFO trigger level. Furthermore, data delivery to the host is guaranteed by a
receive data ready time-out interrupt when data is not received for 4 word lengths as defined by LCR[1:0] plus
12 bits time. This is equivalent to 3.7-4.6 character times. The RHR interrupt is enabled by IER bit-0. See
Figure 5.
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