XR28V384IM48-0A Datasheet, PDF (7/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
default value of the RTSA#/PS_CONF_2E/RS485 pin is ’1’ when the system powers on. Therefore, the default
index port address is 0x2E and the data port address is 0x2F.
TABLE 2: CONFIGURATION PORT SELECTION
RTSA#/PS_CONF_2E/RS485 (PIN 41)
INDEX PORT ADDRESS
DATA PORT ADDRESS
0
0x4E
0x4F
1 (default)
0x2E
0x2F
1.1.2.2
Configuration Entry Key Options
In order to enable the configuration register access mode, the entry key needs to be written consecutively
twice to the index port. The entry key is generated by the power on setting pins RTSB#/PS_CONF_KEY1/
RS485 and RTSC#/PS_CONF_KEY0/RS485.
TABLE 3: CONFIGURATION ENTRY KEY
RTSB#/PS_CONF_KEY1/RS485
(PIN 33)
RTSC#/PS_CONF_KEY0/RS485
(PIN 23)
ENTRY KEY
0
0
0x77
0
1
0xA0
1
0
0x87
1
1
0x67 (Default)
In order to disable the configuration register access mode, 0xAA must be written to the index port.
1.1.2.3 Example
1.1.2.3.1
Index port address 0x2E & Data port address 0x2F (default)
write (0x2E, 0x67);
write (0x2E, 0x67);
//write entry key (0x67) twice to configuration port
//Enable access to the configuration registers
write (0x2E, 0x20);
//Select the DEV_ID_M register
read (0x2F);
//Read the DEV_ID_M register
write (0x2E, 0x21);
//Select the DEV_ID_L register
read (0x2F);
//Read the DEV_ID_L register
write (0x2E, 0x25);
//Select the Clock Select Register
write (0x2F, 0x1);
//Select the input clock frequency 48 MHz
write (0x2E, 0x7);
//Select the LDN register
write (0x2F, 0x1);
//Select the UART Channel B
write (0x2E, 0xF6);
//Select the FIFO Mode Select Register of UART Channel B
write (0x2F, 0x3);
//Set the FIFO size 128 bytes,
//RX trigger level 1, 4, 8, 14 and no delay for THR empty interrupt
write (0x2E, 0x30);
write (0x2F, 0x1);
//Enable the UART Channel B
write (0x2E, 0xAA);
//Disable access to configuration registers
7