XR28V384IM48-0A Datasheet, PDF (22/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
Bits [7:2]: Reserved
2.1.1.7 Port Select Register - Read/Write
This register selects the configuration port.
Bits [1:0]: Select configuration entry key
The default value of these bits are determined by RTSB#/PS_CONF_KEY1/RS485 and RTSC/
PS_CONF_KEY0/RS485. See Table 3 ’Configuration Entry Key’.
x ’00’ = The entry key is 0x77.
x ’01’ = The entry key is 0xA0.
x ’10’ = The entry key is 0x87.
x ’11’ = The entry key is 0x67.
Bits [3:2]: Reserved
Bit [4]: Select configuration port
The default value of this bit is determined by RTSA#/PS_CONF_2E/RS485 pin. See Table 2 ’Configuration
Port Selection’.
x Logic 0 = The configuration port is 0x2E/0x2F.
x Logic 1 = The configuration port is 0x4E/0x4F.
Bits [7:5]: Reserved
2.1.2 Device Configuration Registers
In order to access Device Configuration Register set, the configuration regsiter access mode has to be
enabled. The value in the LDN register determines which device’s configuration register set to access.
Example: if LDN register = 0x02, modifying UART Enable Register (0x30) will modify UART Enable Register
of channel C.
2.1.2.1 UART Registers
2.1.2.1.1
UART Enable Register (ENABLE) - Read/Write
This register enables/disables the UART selected in the LDN register.
Bit [0]: Enable/Disable UART
The default value of this bit is determined by the strapping options. See Table 1 ’UART Power On
Configuration’. This bit can be programmed after power up.
x Logic 0 = Disable the UART selected in LDN register.
x Logic 1 = Enable the UART selected in LDN register.
Bits [7:1]: Reserved
2.1.2.1.2
Base Address High/Low Register - Read/Write
The V384 provides programmable I/O mapped address feature. Configure the MSB/LSB of 16-bit I/O address,
for the UART selected in LDN register, in this register.
Bits [7:0]: MSB of UART base address (0x60)
The default value of this register is determined by the strapping options. See Table 1 ’UART Power On
Configuration’.
22