XR28V384IM48-0A Datasheet, PDF (26/42 Pages) Exar Corporation – 3.3V QUAD LPC UART WITH 128-BYTE FIFO

XR28V384
REV. 1.0.0
3.3V QUAD LPC UART WITH 128-BYTE FIFO
2.1.2.1.8
FIFO Mode Select Register - Read/Write
This register selects FIFO depth and receiver trigger levels.
Bits [1:0]: FIFO size for TX/RX
x ’00’ = FIFO size is 16 bytes.
x ’01’ = FIFO size is 32 bytes.
x ’10’ = FIFO size is 64 bytes.
x ’11’ = FIFO size is 128 bytes.
Bits [3:2]: Reserved
Bits [5:4]: RX trigger level
x ’00’ = RX trigger level is 1, 4, 8, 14 (See Table 13 ’Receive FIFO Trigger Level Selection’).
x ’01’ = RX trigger level is 2, 8, 16, 28 (See Table 13 ’Receive FIFO Trigger Level Selection’).
x ’10’ = RX trigger level is 4, 16, 32, 56 (See Table 13 ’Receive FIFO Trigger Level Selection’).
x ’11’ = RX trigger level is 8, 32, 64, 112 (See Table 13 ’Receive FIFO Trigger Level Selection’).
Note: for Bits[5:4]= ’01’,’10’ and ’11’ make sure correct FIFO size is programmed in Bits[1:0].
Bit [6]: Reserved
Bit [7]: TX holding register (THR) empty delay
x Logic 0 = No delay for THR empty interrupt (default).
x Logic 1 = Delay 1 transmission clock for THR empty interrupt.
2.1.2.2 Watchdog Timer Registers (LDN = 0x08)
2.1.2.2.1
WDT Enable Register - Read/Write
Bit [0]: WDT Enable/Disable
x Logic 0 = Disable the Watchdog Timer.
x Logic 1 = Enable the Watchdog Timer.
After power on or reset, if the pin DTRC#/PS_WDT is sampled HIGH, this bit will be set to ’1’. Otherwise, this
bit will be set to ’0’. See Table 1 ’UART Power On Configuration’.
Bits [7:1]: Reserved
2.1.2.2.2
WDT Base Address High/Low Register - Read/Write
This register indicates the MSB/LSB of watchdog timer base address.
Bits [7:0]: The MSB of watchdog timer base address (0x60).
After power on or reset, if the pin DTRC#/PS_WDT is sampled HIGH, this byte will be set to 0x04. Otherwise,
this bit will be set to 0x00. See Table 1 ’UART Power On Configuration’.
Bits [7:0]: The LSB of watchdog timer base address (0x61) .
After power on or reset, if the pin DTRC#/PS_WDT is sampled HIGH, this byte will be set to 0x42. Otherwise,
this byte will be set to 0x0. See Table 1 ’UART Power On Configuration’.
2.1.2.2.3
WDT IRQ Channel Select Register - Read/Write
This register enables / disables an interrupt request output from the watchdog timer.
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