XRT83L34 Datasheet, PDF (78/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
TABLE 49: ASYNCHRONOUS MODE 1 - INTEL 8051 AND 80188 INTERFACE TIMING
SYMBOL
PARAMETER
MIN
MAX
t₀
Valid Address to CS Falling Edge
t₁
CS Falling Edge to RD Assert
t₂
RD Assert to RDY Assert
NA
RD Pulse Width (t2)
0
-
65
-
-
50
50
-
t₃
CS Falling Edge to WR Assert
t₄
WR Assert to RDY Assert
NA
WR Pulse Width (t2)
65
-
-
50
50
-
t₅
CS Falling Edge to AS Falling Edge
0
-
Reset pulse width - both Motorola and Intel Operations (see Figure 32)
t₉
Reset pulse width
30
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
75