XRT83L34 Datasheet, PDF (5/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
APPLICATIONS .............................................................................................................................................. 1
Figure 1 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Host Mode) ............................................ 1
Figure 2 Block Diagram of the XRT83L34 T1/E1/J1 LIU (Hardware Mode) ................................... 2
FEATURES .................................................................................................................................................... 2
ORDERING INFORMATION ...................................................................................................................... 3
Figure 3 Pin Out of the XRT83L34 .................................................................................................... 4
TABLE OF CONTENTS ....................................................................................................... I
PIN DESCRIPTION BY FUNCTION ................................................................................... 5
RECEIVE SECTIONS ...................................................................................................................................... 5
TRANSMITTER SECTIONS .............................................................................................................................. 7
MICROPROCESSOR INTERFACE ...................................................................................................................... 9
JITTER ATTENUATOR .................................................................................................................................. 12
CLOCK SYNTHESIZER .................................................................................................................................. 13
ALARM FUNCTION//REDUNDANCY SUPPORT ................................................................................................. 14
POWER AND GROUND ................................................................................................................................. 18
FUNCTIONAL DESCRIPTION ......................................................................................... 19
MASTER CLOCK GENERATOR ...................................................................................................................... 19
Figure 4. Two Input Clock Source .................................................................................................. 19
Figure 5. One Input Clock Source .................................................................................................. 19
RECEIVER ........................................................................................................................ 20
RECEIVER INPUT ......................................................................................................................................... 20
TABLE 1: MASTER CLOCK GENERATOR ............................................................................................... 20
RECEIVE MONITOR MODE ........................................................................................................................... 21
RECEIVER LOSS OF SIGNAL (RLOS) ........................................................................................................... 21
Figure 6. Simplified Diagram of -15dB T1/E1 Short Haul Mode and RLOS Condition ............... 21
Figure 7. Simplified Diagram of -29dB T1/E1 Gain Mode and RLOS Condition ......................... 22
Figure 8. Simplified Diagram of -36dB T1/E1 Long Haul Mode and RLOS Condition ............... 22
RECEIVE HDB3/B8ZS DECODER ................................................................................................................ 23
RECOVERED CLOCK (RCLK) SAMPLING EDGE ............................................................................................ 23
Figure 9. Simplified Diagram of Extended RLOS mode (E1 Only) ............................................... 23
Figure 10. Receive Clock and Output Data Timing ....................................................................... 23
JITTER ATTENUATOR .................................................................................................................................. 24
GAPPED CLOCK (JA MUST BE ENABLED IN THE TRANSMIT PATH) ................................................................. 24
TABLE 2: MAXIMUM GAP WIDTH FOR MULTIPLEXER/MAPPER APPLICATIONS ........................................ 24
ARBITRARY PULSE GENERATOR FOR T1 AND E1 .......................................................................................... 25
TRANSMITTER ................................................................................................................. 25
DIGITAL DATA FORMAT ............................................................................................................................... 25
TRANSMIT CLOCK (TCLK) SAMPLING EDGE ................................................................................................ 25
Figure 11. Arbitrary Pulse Segment Assignment .......................................................................... 25
TRANSMIT HDB3/B8ZS ENCODER .............................................................................................................. 26
Figure 12. Transmit Clock and Input Data Timing ........................................................................ 26
TABLE 3: EXAMPLES OF HDB3 ENCODING ........................................................................................... 26
TABLE 4: EXAMPLES OF B8ZS ENCODING ........................................................................................... 26
DRIVER FAILURE MONITOR (DMO) .............................................................................................................. 27
TRANSMIT PULSE SHAPER & LINE BUILD OUT (LBO) CIRCUIT ...................................................................... 27
TABLE 5: RECEIVE EQUALIZER CONTROL AND TRANSMIT LINE BUILD-OUT SETTINGS ........................... 27
TRANSMIT AND RECEIVE TERMINATIONS .................................................................. 29
RECEIVER (CHANNELS 0 - 3) ................................................................................................................... 29
Internal Receive Termination Mode .......................................................................................................... 29
TABLE 6: RECEIVE TERMINATION CONTROL .......................................................................................... 29
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