XRT83L34 Datasheet, PDF (69/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
TABLE 37: MICROPROCESSOR REGISTER #66, BIT DESCRIPTION
D3
SL_1 Slicer Level Control bit 1: This bit and bit D2 control the slic- R/W
0
ing level for the slicer per the following table.
SL_1
0
0
1
1
SL_0
0
1
0
1
Slicer Mode
Normal
Decrease by 5% from Normal
Increase by 5% from Normal
Normal
D2
SL_0 Slicer Level Control bit 0: See description bit D3.
R/W
0
D1
EQG_1 Equalizer Gain Control bit 1: This bit together with bit D0
R/W
0
control the gain of the equalizer as shown in the table below.
EQG_1
0
0
1
1
EQG_0
0
1
0
1
Equalizer Gain
Normal
Reduce Gain by 1 dB
Reduce Gain by 3 dB
Normal
D0
EQG_0 Equalizer Gain Control bit 0: See description of bit D1
R/W
0
66