XRT83L34 Datasheet, PDF (17/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
SIGNAL NAME
MCLKT1
MCLKOUT
PIN #
33
36
TYPE
I
O
DESCRIPTION
T1 Master Clock Input
This signal is an independent 1.544MHz clock for T1 systems with required
accuracy of better than ±50ppm and duty cycle of 40% to 60%. MCLKT1
input is used in the T1 mode.
NOTES:
1. All channels of the XRT83L34 must be operated at the same clock
rate, either T1, E1 or J1.
2. See pin 32 description for further explanation for the usage of this
pin.
3. Internally pulled “Low” with a 50kΩ resistor.
Synthesized Master Clock Output
This signal is the output of the Master Clock Synthesizer PLL which is at T1
or E1 rate based upon the mode of operation.
ALARM FUNCTION//REDUNDANCY SUPPORT
SIGNAL NAME
GAUGE
DMO_0
DMO_1
DMO_2
DMO_3
ATAOS
µPCLK
PIN #
87
64
65
66
67
50
TYPE
I
O
DESCRIPTION
Twisted Pair Cable Wire Gauge Select - Hardware mode
Connect this pin "High" to select 26 Gauge wire. Connect this pin “Low” to
select 22 and 24 gauge wire for all channels.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Driver Failure Monitor Channel _0
This pin transitions "High" if a short circuit condition is detected in the trans-
mit driver of Channel _0, or no transmit output pulse is detected for more
than 128 TCLK_0 cycles.
Driver Failure Monitor Channel _1
Driver Failure Monitor Channel _2
Driver Failure Monitor Channel _3
I
Automatic Transmit “All Ones” Pattern - Hardware Mode
A "High" level on this pin enables the automatic transmission of an "All Ones"
AMI pattern from the transmitter of any channel that the receiver of that
channel has detected an LOS condition. A "Low" level on this pin disables
this function.
NOTE: All channels share the same ATAOS input control function.
Microprocessor Clock Input - Host Mode
See “Microprocessor Clock Input - Host Mode” on page 10.
NOTE: This pin is internally pulled “Low” for asynchronous microprocessor
interface when no clock is present.
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