XRT83L34 Datasheet, PDF (14/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
SIGNAL NAME
A[6]
A[5]
A[4]
A[3]
A[2]
A[1]
A[0]
JASEL1
JASEL0
EQC4
EQC3
EQC2
EQC1
EQC0
INT
TRATIO
PIN #
57
58
59
60
61
62
63
57
58
59
60
61
62
63
119
119
TYPE
I
I
DESCRIPTION
Microprocessor Address Pins - Host mode:
Microprocessor Interface Address Bus[6]
Microprocessor Interface Address Bus[5]
Microprocessor Interface Address Bus[4]
Microprocessor Interface Address Bus[3]
Microprocessor Interface Address Bus[2]
Microprocessor Interface Address Bus[1]
Microprocessor Interface Address Bus[0]
Jitter Attenuator Select Pins - Hardware Mode
Jitter Attenuator select pin 1
Jitter Attenuatore select pin 0
See “Jitter Attenuator” on page 12.
Equalizer Control Pins - Hardware Mode
Equalizer Control Input pin 4
Equalizer Control Input pin 3
Equalizer Control Input pin 2
Equalizer Control Input pin 1
Equalizer Control Input pin 0
Pins EQC[4:0] select the Receive Equalizer and Transmitter Line Build Out.
See “Alarm Function//Redundancy Support” on page 14.
NOTE: Internally pulled “Low” with a 50kΩ resistor.
Interrupt Output - Host Mode
This pin goes “Low” to indicate an alarm condition has occurred within the
device. Interrupt generation can be globally disabled by setting the GIE bit to
"0" in the command control register.
Transmitter Transformer Ratio Select - Hardware mode
The function of this pin is to select the transmitter transformer ratio. See
“Alarm Function//Redundancy Support” on page 14.
NOTE: This pin is an open drain output and requires an external 10kΩ pull-
up resistor.
11