XRT83L34 Datasheet, PDF (57/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION
REGISTER ADDRESS
0000101
0010101
0100101
0110101
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
RO
0
D6
DMO_n Driver Monitor Output: This bit is set to a “1” to indicate
RO
0
transmit driver failure is detected. The value of this bit is based
on the current status of DMO for the corresponding channel. If
the DMOIE bit is enabled, any transition on this bit will gener-
ate an Interrupt.
D5
FLS_n FiFO Limit Status: This bit is set to a “1” to indicate that the jit- RO
0
ter attenuator read/write FIFO pointers are within +/- 3 bits. If
the FLSIE bit is enabled, any transition on this bit will generate
an Interrupt.
D4
LCV_n Line Code Violation: This bit is set to a “1” to indicate that the RO
0
receiver of channel n is currently detecting a Line Code Viola-
tion or an excessive number of zeros in the B8ZS or HDB3
modes. If the LCVIE bit is enabled, any transition on this bit will
generate an Interrupt.
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