XRT83L34 Datasheet, PDF (56/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION
REGISTER ADDRESS
0000100
0010100
0100100
0110100
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
Reserved
RO
0
D6
DMOIE_n DMO Interrupt Enable: Writing a “1” to this bit enables DMO R/W
0
interrupt generation, writing a “0” masks it.
D5
FLSIE_n FIFO Limit Status Interrupt Enable: Writing a “1” to this bit
R/W
0
enables interrupt generation when the FIFO limit is within to 3
bits, writing a “0” to masks it.
D4
LCVIE_n Line Code Violation Interrupt Enable: Writing a “1” to this bit R/W
0
enables Line Code Violation interrupt generation, writing a “0”
masks it.
D3
NLCDIE_n Network Loop-Code Detection Interrupt Enable: Writing a R/W
0
“1” to this bit enables Network Loop-code detection interrupt
generation, writing a “0” masks it.
D2
AISDIE_n AIS Interrupt Enable: Writing a “1” to this bit enables Alarm
R/W
0
Indication Signal detection interrupt generation, writing a “0”
masks it.
D1
RLOSIE_n Receive Loss of Signal Interrupt Enable: Writing a “1” to this R/W
0
bit enables Loss of Receive Signal interrupt generation, writing
a “0” masks it.
D0
QRPDIE_n QRSS Pattern Detection Interrupt Enable: Writing a “1” to
R/W
0
this bit enables QRSS pattern detection interrupt generation,
writing a “0” masks it.
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