XRT83L34 Datasheet, PDF (66/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
CLOCK SELECT REGISTER
The input clock source is used to generate all the necessary clock references internally to the LIU. The
microprocessor timing is derived from a PLL output which is chosen by programming the Clock Select Bits and
the Master Clock Rate in register 0x41h. Therefore, if the clock selection bits or the MCLRATE bit are being
programmed, the frequency of the PLL output will be adjusted accordingly. During this adjustment, it is
important to "Not" write to any other bit location within the same register while selecting the input/output clock
frequency. For best results, when bits D[6:3] are being changed, the other bits D[7] and D[2:0] as shown in
Figure 25. should retain their previous values.
FIGURE 25. REGISTER 0X81H SUB REGISTERS
D7
D6
D5
D4
D3
D2
D1
D0
E1arben Clock Selection Bits
ExLOS, ICT
Programming Examples:
Example 1: Changing bits D[6:3]
If bits D[6:3] are the only values within the register that will change in a WRITE process, the microprocessor
only needs to initiate ONE write operation.
Example 2: Changing bits D[7] and D[2:0]
If bits D[7] and D[2:0] are the only values within the register that will change in a WRITE process, the
microprocessor only needs to initiate ONE write operation.
Example 3: Changing bits within D[6:3] and the other bits
In this scenario, one must initiate TWO write operations such that bits D[6:3] and the other bits do not change
within ONE write cycle. It is recommended that bits D[6:0] and the other bits be treated as two independent
sub-registers. One can either change the clock selection bits and then change bits D[7] and D[2:0] on the
SECOND write, or vice-versa. No order or sequence is necessary.
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