XRT83L34 Datasheet, PDF (77/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
REV. P1.3.4
PRELIMINARY
FIGURE 29. RECEIVE CLOCK AND OUTPUT DATA TIMING
R_DY
RCLK_R
RCLK_F
RCLK
RPOS
or
RNEG
R_HO
MICROPROCESSOR INTERFACE I/O TIMING
INTEL INTERFACE TIMING - ASYNCHRONOUS
The signals used for the Intel microprocessor interface are: Address Latch Enable (ALE), Read Enable (RD),
Write Enable (WR), Chip Select (CS), Address and Data bits. The microprocessor interface uses minimum ex-
ternal glue logic and is compatible with the timings of the 8051 or 80C188 with an 8-16 MHz clock frequency,
and with the timings of x86 or i960 family or microprocessors. The interface timing shown in Figure 30 and
Figure 32 is described in Table 49.
FIGURE 30. INTEL ASYNCHRONOUS PROGRAMMED I/O INTERFACE TIMING
ALE_AS
A D D R [6 :0 ]
CS
D A T A [7 :0 ]
RD_DS
W R _R /W
RDY_DTACK
t₀
t₅
t₁
READ OPERATION
Valid Address
Valid Data for Readback
t₂
WRITE OPERATION
t₀
t₅
Valid Address
Data Available to W rite Into the LIU
t₃
t₄
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