XRT83L34 Datasheet, PDF (50/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION
REGISTER ADDRESS
0000001
0010001
0100001
0110001
CHANNEL_n
CHANNEL_0
CHANNEL_1
CHANNEL_2
CHANNEL_3
FUNCTION
REGISTER
TYPE
RESET
VALUE
BIT #
NAME
D7
RXTSEL_n Receiver Termination Select: In Host mode, this bit is used R/W
0
to select between the internal and external line termination
modes for the receiver according to the following table;
RXTSEL
0
1
RX Termination
External
Internal
D6
TXTSEL_n Transmit Termination Select: In Host mode, this bit is used R/W
0
to select between the internal and external line termination
modes for the transmitter according to the following table;
TXTSEL
0
1
TX Termination
External
Internal
D5
TERSEL1_n Termination Impedance Select1:
R/W
0
In Host mode and in internal termination mode, (TXTSEL = “1”
and RXTSEL = “1”) TERSEL[1:0] control the transmit and
receive termination impedance according to the following
table;
TERSEL1 TERSEL0
0
0
0
1
1
0
1
1
Termination
100Ω
110Ω
75Ω
120Ω
In the internal termination mode, the receiver termination of
each receiver is realized completely by internal resistors or by
the combination of internal and one fixed external resistor.
In the internal termination mode, the transmitter output should
be AC coupled to the transformer.
D4
TERSEL0_n Termination Impedance Select bit 0:
See description of bit D5 for the function of this bit.
R/W
0
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