XRT83L34 Datasheet, PDF (6/82 Pages) Exar Corporation – QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR

XRT83L34
QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
PRELIMINARY
REV. P1.3.4
Figure 13. Simplified Diagram for the Internal Receive and Transmit Termination Mode ........ 29
TABLE 7: RECEIVE TERMINATIONS ....................................................................................................... 30
Figure 14. Simplified Diagram for T1 in the External Termination Mode (RXTSEL= 0) ............. 30
TRANSMITTER (CHANNELS 0 - 3) ............................................................................................................ 31
Transmit Termination Mode ...................................................................................................................... 31
External Transmit Termination Mode ........................................................................................................ 31
Figure 15. Simplified Diagram for E1 in External Termination Mode (RXTSEL= 0) ................... 31
TABLE 8: TRANSMIT TERMINATION CONTROL ....................................................................................... 31
TABLE 9: TERMINATION SELECT CONTROL .......................................................................................... 31
REDUNDANCY APPLICATIONS ............................................................................................................. 32
TABLE 10: TRANSMIT TERMINATION CONTROL ..................................................................................... 32
TABLE 11: TRANSMIT TERMINATIONS ................................................................................................... 32
TYPICAL REDUNDANCY SCHEMES ..................................................................................................... 33
Figure 16. Simplified Block Diagram of the Transmit Section for 1:1 & 1+1 Redundancy ....... 34
Figure 17. Simplified Block Diagram - Receive Section for 1:1 and 1+1 Redundancy ............. 34
Figure 18. Simplified Block Diagram - Transmit Section for N+1 Redundancy ......................... 35
Figure 19. Simplified Block Diagram - Receive Section for N+1 Redundancy .......................... 36
PATTERN TRANSMIT AND DETECT FUNCTION ............................................................................................... 37
TRANSMIT ALL ONES (TAOS) .................................................................................................................... 37
NETWORK LOOP CODE DETECTION AND TRANSMISSION .............................................................................. 37
TABLE 12: PATTERN TRANSMISSION CONTROL ..................................................................................... 37
TABLE 13: LOOP-CODE DETECTION CONTROL ..................................................................................... 37
TRANSMIT AND DETECT QUASI-RANDOM SIGNAL SOURCE (TDQRSS) ......................................................... 38
LOOP-BACK MODES ................................................................................................................................... 39
LOCAL ANALOG LOOP-BACK (ALOOP) ....................................................................................................... 39
TABLE 14: LOOP-BACK CONTROL IN HARDWARE MODE ........................................................................ 39
TABLE 15: LOOP-BACK CONTROL IN HOST MODE ................................................................................. 39
Figure 20. Local Analog Loop-back signal flow ........................................................................... 39
REMOTE LOOP-BACK (RLOOP) ................................................................................................................. 40
Figure 21. Remote Loop-back mode with jitter attenuator selected in receive path ................. 40
Figure 22. Remote Loop-back mode with jitter attenuator selected in Transmit path .............. 40
DIGITAL LOOP-BACK (DLOOP) .................................................................................................................. 41
DUAL LOOP-BACK ...................................................................................................................................... 41
Figure 23. Digital Loop-back mode with jitter attenuator selected in Transmit path ................ 41
Figure 24. Signal flow in Dual loop-back mode ............................................................................ 41
MICROPROCESSOR PARALLEL INTERFACE .............................................................. 42
TABLE 16: MICROPROCESSOR INTERFACE SIGNAL DESCRIPTION ........................................................... 42
MICROPROCESSOR REGISTER TABLES ........................................................................................................ 43
TABLE 17: MICROPROCESSOR REGISTER ADDRESS ............................................................................. 43
TABLE 18: MICROPROCESSOR REGISTER BIT DESCRIPTION ................................................................. 43
MICROPROCESSOR REGISTER DESCRIPTIONS ............................................................................................. 46
TABLE 19: MICROPROCESSOR REGISTER #0, BIT DESCRIPTION ........................................................... 46
TABLE 20: MICROPROCESSOR REGISTER #1, BIT DESCRIPTION ........................................................... 47
TABLE 21: MICROPROCESSOR REGISTER #2, BIT DESCRIPTION ........................................................... 49
TABLE 22: MICROPROCESSOR REGISTER #3, BIT DESCRIPTION ........................................................... 51
TABLE 23: MICROPROCESSOR REGISTER #4, BIT DESCRIPTION ........................................................... 53
TABLE 24: MICROPROCESSOR REGISTER #5, BIT DESCRIPTION ........................................................... 54
TABLE 25: MICROPROCESSOR REGISTER #6, BIT DESCRIPTION ........................................................... 56
TABLE 26: MICROPROCESSOR REGISTER #7, BIT DESCRIPTION ........................................................... 57
TABLE 27: MICROPROCESSOR REGISTER #8, BIT DESCRIPTION ........................................................... 58
TABLE 28: MICROPROCESSOR REGISTER #9, BIT DESCRIPTION ........................................................... 58
TABLE 29: MICROPROCESSOR REGISTER #10, BIT DESCRIPTION ......................................................... 59
TABLE 30: MICROPROCESSOR REGISTER #11, BIT DESCRIPTION ......................................................... 59
TABLE 31: MICROPROCESSOR REGISTER #12, BIT DESCRIPTION ......................................................... 60
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