XRT75R03D_06 Datasheet, PDF (69/135 Pages) Exar Corporation – EXAR DATA SHEET FORMAT TEMPLATES

REV. 1.0.4
XRT75R03D
THREE CHANNEL E3/DS3/STS-1 LINE
BIT 7
R/O
1
TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F)
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
Chip Revision Number Value
R/O
R/O
R/O
R/O
R/O
R/O
0
0
0
X
X
X
BIT 0
R/O
X
BIT NUMBER
7-0
NAME
Chip Revision
Number Value
TYPE
R/O
DEFAULT
VALUE
DESCRIPTION
0x8#
Chip Revision Number Value:
This READ-ONLY register contains a value that represents
the current revision of this XRT75R03D. This revision num-
ber will always be in the form of "0x8#", where "#" is a hexa-
decimal value that specifies the current revision of the chip.
For example, the very first revision of this chip will contain
the value "0x81".
THE PER-CHANNEL REGISTERS
The XRT75R03D consists of 21 per-Channel Registers. Table 23 presents the overall Register Map with the
Per-Channel Registers shaded.
TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU W/
JITTER ATTENUATOR IC
ADDRESS
COMMAND REGISTER
TYPE
REGISTER NAME
0x00
CR0
R/W APS/Redundancy Control Register
CHANNEL 0 CONTROL REGISTERS
0x01
CR1
R/O Source Level Interrupt Enable Register - Channel 0
0x02
CR2
R/W Source Level Interrupt Status Register Channel 0
0x03
CR3
R/O Alarm Status Register - Channel 0
0x04
CR4
R/W Transmit Control Register - Channel 0
0x05
CR5
R/W Receive Control Register - Channel 0
0x06
CR6
R/W Channel Control Register - Channel 0
0x07
CR7
R/W Jitter Attenuator Control Register - Channel 0
CHANNEL 1 CONTROL REGISTERS
0x08
CR8
R/O Reserved
0x09
CR9
R/W Source Level Interrupt Enable Register - Channel 1
0x0A
CR10
RUR Source Level Interrupt Status Register - Channel 1
0x0B
CR11
R/O Alarm Status Register - Channel 1
65