XRT75R03D_06 Datasheet, PDF (127/135 Pages) Exar Corporation – EXAR DATA SHEET FORMAT TEMPLATES

REV. 1.0.4
XRT75R03D
THREE CHANNEL E3/DS3/STS-1 LINE
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
R/O
0
BIT 6
Unused
R/O
0
BIT 5
R/O
0
BIT 4
BIT 3
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
R/W
R/W
0
0
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/W
R/W
R/W
0
1
1
• If the XRT75R03D has been configured to operate in the Hardware Mode.
Then the user should tie pin 43 (JATx/JARx*) to "1".
e. Enable the "SONET APS Recovery Time" Mode
Finally, if the user intends to use the XRT75R03D in an Application that is required to reacquire proper SONET
and DS3 traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253-
CORE), then the user should set Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator
Control" Register, to "0" as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
R/O
0
BIT 6
Unused
R/O
0
BIT 5
R/O
0
BIT 4
BIT 3
SONET APS
Recovery
Time
DisableCh_n
JA RESET
Ch_n
R/W
R/W
0
0
BIT 2
JA1 Ch_n
BIT 1
JA in Tx Path
Ch_n
BIT 0
JA0 Ch_n
R/W
R/W
R/W
0
0
1
NOTES:
1. The ability to disable the "SONET APS Recovery Time" mode is only available if the XRT75R03D is operating in
the Host Mode. If the XRT75R03D is operating in the "Hardware" Mode, then this "SONET APS Recovery Time
Mode" feature will always be enabled.
2. The "SONET APS Recovery Time" mode will be discussed in greater detail in “Section 10.8.3, How does the
XRT75R03D permit the user to comply with the SONET APS Recovery Time requirements of
50ms (per Telcordia GR-253-CORE)?” on page 127.
10.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device)
prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the XRT75R03D
In order to minimize the effects of "Clock-Gapping" Jitter within the DS3 signal that is ultimately transmitted to
the DS3 Line (or facility), we recommend that some "pre-processing" of the "Data-Signals" and "Clock-Signals"
(which are output from the Mapper device) be implemented prior to routing these signals to the "Transmit
Inputs" of the XRT75R03D.
10.8.2.1 SOME NOTES PRIOR TO STARTING THIS DISCUSSION:
123