XRT75R03D_06 Datasheet, PDF (63/135 Pages) Exar Corporation – EXAR DATA SHEET FORMAT TEMPLATES

XRT75R03D
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
THE GLOBAL/CHIP-LEVEL REGISTERS
The register set, within the XRT75R03D consists of five "Global" or "Chip-Level" Registers and 21 per-Channel
Registers. This section will present detailed information on the Global Registers.
ADDRESS
0x00
0x01 - 0x1F
0x20
0x21
0x22 - 0x3D
0x3E
0x3F
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS
COMMAND REGISTER
TYPE
REGISTER NAME
CR0
R/W
APS/Redundancy Control Register
Bank of Per-Channel Registers
CR32
R/W
Block Level Interrupt Enable Register
CR33
R/O
Block Level Interrupt Status Register
Reserved Registers
CR62
R/O
Device/Part Number Register
CR63
R/O
Chip Revision Number Register
REGISTER DESCRIPTION - GLOBAL REGISTERS
TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Reserved RxONCh 2 RxON Ch 1 RxON Ch 0 Reserved TxON Ch 2 TxON Ch 1 TxON Ch 0
R/O
R/W
R/W
R/W
R/O
R/W
R/W
R/W
0
0
0
0
0
0
0
0
BIT
NUMBER
NAME
7
Reserved
6
RxON Ch 2
TYPE
R/O
R/W
DEFAULT
VALUE
0
0
DESCRIPTION
Receiver Section ON - Channel 2
This READ/WRITE bit-field is used to either turn on or turn off the
Receive Section of Channel 2. If the user turns on the Receive Sec-
tion, then Channel 2 will begin to receive the incoming DS3, E3 or
STS-1 data-stream via the RTIP_2 and RRING_2 input pins.
Conversely, if the user turns off the Receive Section, then the entire
Receive Section (e.g., AGC and Receive Equalizer Block, Clock
Recovery PLL, etc) will be powered down.
0 - Shuts off the Receive Section of Channel 2.
1 - Turns on the Receive Section of Channel 2.
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