XRT75R03D_06 Datasheet, PDF (5/135 Pages) Exar Corporation – EXAR DATA SHEET FORMAT TEMPLATES

XRT75R03D
REV. 1.0.4
THREE CHANNEL E3/DS3/STS-1 LINE
6.0 THE RECEIVER SECTION: ................................................................................................................. 44
6.1 AGC/EQUALIZER: .......................................................................................................................................... 44
6.1.1 INTERFERENCE TOLERANCE: ................................................................................................................................ 45
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1................................................................................................ 45
FIGURE 19. INTERFERENCE MARGIN TEST SET UP FOR E3. ............................................................................................................ 46
TABLE 9: INTERFERENCE MARGIN TEST RESULTS ........................................................................................................................... 46
6.2 CLOCK AND DATA RECOVERY: .................................................................................................................. 46
6.3 B3ZS/HDB3 DECODER: ................................................................................................................................ 47
6.4 LOS (LOSS OF SIGNAL) DETECTOR: ......................................................................................................... 47
6.4.1 DS3/STS-1 LOS CONDITION: .................................................................................................................................... 47
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3
AND STS-1 APPLICATIONS)............................................................................................................................................. 47
DISABLING ALOS/DLOS DETECTION: .......................................................................................................... 47
6.4.2 E3 LOS CONDITION:.................................................................................................................................................. 47
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.......................................................................................... 48
FIGURE 21. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775. ......................................................................................... 48
6.4.3 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 49
7.0 JITTER: ................................................................................................................................................ 49
7.1 JITTER TOLERANCE - RECEIVER: .............................................................................................................. 49
FIGURE 22. JITTER TOLERANCE MEASUREMENTS ........................................................................................................................... 49
7.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS:............................................................................................... 49
FIGURE 23. INPUT JITTER TOLERANCE FOR DS3/STS-1................................................................................................................ 50
7.1.2 E3 JITTER TOLERANCE REQUIREMENTS:............................................................................................................. 50
FIGURE 24. INPUT JITTER TOLERANCE FOR E3 .............................................................................................................................. 50
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) .................................................................. 51
7.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: ...................................................................................... 51
TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................................................ 51
7.3 JITTER ATTENUATOR: ................................................................................................................................. 51
TABLE 13: JITTER TRANSFER PASS MASKS .................................................................................................................................... 52
FIGURE 25. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE................................................................ 52
7.3.1 JITTER GENERATION: .............................................................................................................................................. 52
8.0 SERIAL HOST INTERFACE: ............................................................................................................... 52
TABLE 14: FUNCTIONS OF SHARED PINS ......................................................................................................................................... 53
TABLE 15: XRT75R03D REGISTER MAP - QUICK LOOK ................................................................................................................. 54
Legend: ..................................................................................................................................................................... 57
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU IC57
TABLE 16: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
57
THE GLOBAL/CHIP-LEVEL REGISTERS ................................................................................................ 59
TABLE 17: LIST AND ADDRESS LOCATIONS OF GLOBAL REGISTERS ................................................................................................. 59
REGISTER DESCRIPTION - GLOBAL REGISTERS ............................................................................... 59
TABLE 18: APS/REDUNDANCY CONTROL REGISTER - CR0 (ADDRESS LOCATION = 0X00) ............................................................... 59
TABLE 19: BLOCK LEVEL INTERRUPT ENABLE REGISTER - CR32 (ADDRESS LOCATION = 0X20)....................................................... 62
TABLE 20: BLOCK LEVEL INTERRUPT STATUS REGISTER - CR33 (ADDRESS LOCATION = 0X21)....................................................... 63
TABLE 21: DEVICE/PART NUMBER REGISTER - CR62 (ADDRESS LOCATION = 0X3E) ....................................................................... 64
TABLE 22: CHIP REVISION NUMBER REGISTER - CR63 (ADDRESS LOCATION = 0X3F)..................................................................... 65
THE PER-CHANNEL REGISTERS ........................................................................................................... 65
TABLE 23: COMMAND REGISTER ADDRESS MAP, WITHIN THE XRT75R03D 3-CHANNEL DS3/E3/STS-1 LIU W/ JITTER ATTENUATOR IC
65
REGISTER DESCRIPTION - PER CHANNEL REGISTERS .................................................................... 67
TABLE 24: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X01 .............................................. 67
TABLE 25: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X02 .............................................. 69
TABLE 26: ALARM STATUS REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X03............................................................................. 71
TABLE 27: TRANSMIT CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X04 ..................................................................... 76
TABLE 28: RECEIVE CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X05 ....................................................................... 79
TABLE 29: CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ...................................................................... 81
TABLE 30: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 ..................................................... 84
9.0 DIAGNOSTIC FEATURES: ................................................................................................................. 86
9.1 PRBS GENERATOR AND DETECTOR: ........................................................................................................ 86
FIGURE 26. PRBS MODE ............................................................................................................................................................. 86
9.2 LOOPBACKS: ................................................................................................................................................ 86
9.2.1 ANALOG LOOPBACK:............................................................................................................................................... 86
FIGURE 27. ANALOG LOOPBACK..................................................................................................................................................... 87
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